公开(公告)号：US07237175B2

公开(公告)日：2007-06-26

申请号：US10193319

申请日：2002-07-12

申请人： Makoto Hatakenaka ,  Koji Nii ,  Atsuo Mangyo ,  Takeshi Fujino

发明人： Makoto Hatakenaka ,  Koji Nii ,  Atsuo Mangyo ,  Takeshi Fujino

IPC分类号： G11C29/00

CPC分类号： G06F11/1012

摘要： When to a memory cell array 21 a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory units 31 to 37 each of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory units 31 to 37, respectively. In the 7-bit data, the written bit data has an interval of four bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.

摘要翻译： 对于存储单元阵列21，对其中将3位的奇偶校验位加到4位的数据的7位数据执行读/写操作，关于7位的每一位执行错误校正 数据。 存储单元阵列被分成存储器单元31至37，每个存储单元具有沿着字线的方向布置的四位。 在将7位数据写入存储单元阵列时，7位数据彼此不同的位被分别写入存储单元31至37中的字线方向的写入位数据。 在7位数据中，写入位数据的间隔为4位。 误差校正电路对7位数据中的每一个执行7位数据的纠错。

公开(公告)号：US07224574B2

公开(公告)日：2007-05-29

申请号：US11373258

申请日：2006-03-13

申请人： Takeshi Fujino ,  Byoungju Lee

发明人： Takeshi Fujino ,  Byoungju Lee

IPC分类号： H01G9/00

CPC分类号： H01G9/022 ,  H01G11/32 ,  H01G11/60 ,  Y02E60/13 ,  Y02T10/7022

摘要： An electric double layer capacitor in which gas generation due to decomposition of a solvent of an electrolyte solution in the capacitor is reduced and performance maintaining ratio is superior, is provided by a method which is different from a method of adding additives to the electrolyte solution. The electric double layer capacitor has activated carbon polarizing electrodes and a non-water-based solvent, and a positive electrode of the activated carbon polarizing electrodes contains an antacid agent.

摘要翻译： 通过与电解质溶液中添加添加剂的方法不同的方法，提供了电容器中由于电解质溶液的溶剂分解而产生气体而保持性能优异的双电层电容器。 双电层电容器具有活性碳极化电极和非水性溶剂，活性碳极化电极的正极含有抗酸剂。

公开(公告)号：US07139208B2

公开(公告)日：2006-11-21

申请号：US11165273

申请日：2005-06-24

申请人： Kazutami Arimoto ,  Hiroki Shimano ,  Takeshi Fujino ,  Takeshi Hashizume

发明人： Kazutami Arimoto ,  Hiroki Shimano ,  Takeshi Fujino ,  Takeshi Hashizume

IPC分类号： G11C7/20 ,  G11C5/14

CPC分类号： G11C29/006 ,  G11C7/1045 ,  G11C11/401 ,  G11C11/406 ,  G11C11/4087 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C29/83 ,  G11C2029/1204 ,  G11C2207/104 ,  G11C2211/4013 ,  G11C2211/5641

摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

公开(公告)号：US20060209493A1

公开(公告)日：2006-09-21

申请号：US11373258

申请日：2006-03-13

申请人： Takeshi Fujino ,  Byoungju Lee

发明人： Takeshi Fujino ,  Byoungju Lee

IPC分类号： H01G4/228

CPC分类号： H01G9/022 ,  H01G11/32 ,  H01G11/60 ,  Y02E60/13 ,  Y02T10/7022

摘要： An electric double layer capacitor in which gas generation due to decomposition of a solvent of an electrolyte solution in the capacitor is reduced and performance maintaining ratio is superior, is provided by a method which is different from a method of adding additives to the electrolyte solution. The electric double layer capacitor has activated carbon polarizing electrodes and a non-water-based solvent, and a positive electrode of the activated carbon polarizing electrodes contains an antacid agent.

摘要翻译： 通过与向电解液中添加添加剂的方法不同的方法，提供了电容器中由于电解质溶液的溶剂分解而产生气体而保持性能优异的电双层电容器。 双电层电容器具有活性碳极化电极和非水性溶剂，活性碳极化电极的正极含有抗酸剂。

公开(公告)号：US07047461B2

公开(公告)日：2006-05-16

申请号：US10322676

申请日：2002-12-19

申请人： Akira Yamazaki ,  Takeshi Fujino ,  Atsuo Mangyo

发明人： Akira Yamazaki ,  Takeshi Fujino ,  Atsuo Mangyo

IPC分类号： G11C29/00

CPC分类号： G11C29/1201 ,  G11C29/24

摘要： A semiconductor integrated circuit device includes test data output nodes arranged in a width of a plurality of bits and an internal data bus, greater in bit width than the test data output nodes, for transferring internal data. A predetermined number of bits of the internal data on the internal data bus are compared with bits of test expected value data equal in bit width to the test data output nodes for each bit. The predetermined number of bits of the internal data are selected in accordance with a test address signal. The bits selected is compared with the respective bits of the test expected valued data. Data indicating respective comparison results are output to the test data output nodes in parallel.

摘要翻译： 半导体集成电路器件包括以多个位宽度布置的测试数据输出节点和内部数据总线，其位宽比测试数据输出节点更大，用于传送内部数据。 将内部数据总线上的内部数据的预定数量的比特与针对每个比特的测试数据输出节点的比特宽度相等的测试期望值数据的比特进行比较。 根据测试地址信号选择内部数据的预定位数。 所选择的比较与测试期望值数据的各个比特。 指示各个比较结果的数据被并行地输出到测试数据输出节点。

公开(公告)号：US06507532B1

公开(公告)日：2003-01-14

申请号：US09722687

申请日：2000-11-28

申请人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

发明人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C8/18 ,  G11C11/4087

摘要： A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.

摘要翻译： 中央行相关控制电路与外部时钟信号异步地将内部行地址信号发送到存储器存储体中的每个存储器子块，并且与一个内部时钟信号同步地锁存用于指定存储器子块的块选择信号 时钟周期，用于传输到每个存储器子块。 备用确定电路与时钟信号异步地执行备用确定。 可以提供容易适应银行扩张的半导体存储器件，而不增加芯片面积并且能够实现高速存取。

公开(公告)号：US06272034B1

公开(公告)日：2001-08-07

申请号：US09606402

申请日：2000-06-29

申请人： Mitsuya Kinoshita ,  Fukashi Morishita ,  Kazutami Arimoto ,  Takeshi Fujino ,  Tetsushi Tanizaki ,  Takahiro Tsuruda ,  Teruhiko Amano ,  Mako Kobayashi

发明人： Mitsuya Kinoshita ,  Fukashi Morishita ,  Kazutami Arimoto ,  Takeshi Fujino ,  Tetsushi Tanizaki ,  Takahiro Tsuruda ,  Teruhiko Amano ,  Mako Kobayashi

IPC分类号： G11C502

CPC分类号： G11C5/025

摘要： A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.

摘要翻译： 控制存储器单元的操作的控制电路部分集中在中心部分，并且热辐射板通过粘合剂放置在其上。 具有MPU等的功能的半导体集成电路经由凸块电极放置在控制电路部分上方。 控制电路部分和存储块分别形成在分开的芯片上。

公开(公告)号：US6151244A

公开(公告)日：2000-11-21

申请号：US176029

申请日：1998-10-21

申请人： Takeshi Fujino ,  Kazutami Arimoto

发明人： Takeshi Fujino ,  Kazutami Arimoto

IPC分类号： H01L21/8247 ,  G11C11/401 ,  G11C11/4074 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/24

CPC分类号： G11C11/401 ,  G11C11/4074

摘要： Memory cell minimum units (MCU) formed of multi-bit one transistor/one capacitor type memory cells are repeatedly arranged in a column direction, and bit line contacts (BCT) are shifted in the column direction relative to a row direction. The bit line contacts are repeatedly shifted with a prescribed number of bit lines as a unit. A set of a read bit line onto which memory cell data are read and a reference bit line supplying a reference potential can be obtained by controlling the voltage of cell plate lines and bit lines for each set of bit lines. Accordingly, a memory cell occupation area can be reduced and sensing operation in the folded bit line arrangement is possible. Consequently, a memory cell occupation area per one bit can be dramatically reduced and sensing operation in the folded bit line arrangement can be performed.

摘要翻译： 由多位一晶体管/一电容型存储单元形成的存储单元最小单元（MCU）沿列方向重复排列，并且位线接触（BCT）相对于行方向在列方向上偏移。 位线接点以规定数量的位线为单位重复移位。 通过控制每组位线的单元板线和位线的电压，可以获得读取存储单元数据的读取位线和提供参考电位的参考位线的集合。 因此，可以减小存储器单元占用面积，并且折叠位线布置中的感测操作是可能的。 因此，可以显着减少每一位的存储单元占用面积，并且可以执行折叠位线布置中的感测操作。

公开(公告)号：US5966340A

公开(公告)日：1999-10-12

申请号：US960286

申请日：1997-10-29

申请人： Takeshi Fujino ,  Masaki Tsukude

发明人： Takeshi Fujino ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C7/18 ,  G11C8/14 ,  G11C11/401 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/18 ,  G11C8/14

摘要： Conductive lines for electrostatic shielding including at least one signal line are arranged between a global data I/O bus line and a ground line transmitting a ground voltage to a nonselected word line through a sub-decoder. Capacitive coupling between bus lines included in the global data I/O bus and the ground line is suppressed, and floating up of a ground voltage on the nonselected word line is prevented.

摘要翻译： 包括至少一条信号线的用于静电屏蔽的导电线被布置在全局数据I / O总线与通过子解码器将接地电压发送到非选择字线的接地线之间。 包含在全局数据I / O总线和地线之间的总线之间的电容耦合被抑制，并且防止非选定字线上的接地电压浮起。

公开(公告)号：US5960253A

公开(公告)日：1999-09-28

申请号：US899814

申请日：1997-07-24

申请人： Takeshi Fujino

发明人： Takeshi Fujino

IPC分类号： H01L21/3205 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L21/00

CPC分类号： H01L27/10897

摘要： A method of manufacturing a semiconductor memory device includes a first step of forming a plurality of memory cells with a redundancy portion through fine patterning, a second step of searching a defect in masks used in the fine patterning and a third step of forming offset via holes so as to interconnect the redundancy portion instead of a defective portion identified by an inspection in non-fine patterning conducted after the fine patterning.

摘要翻译： 一种制造半导体存储器件的方法包括：通过精细图案化形成具有冗余部分的多个存储单元的第一步骤，在精细图案化中使用的掩模中搜索缺陷的第二步骤和形成偏移通孔的第三步骤 以便在精细图案化之后进行的非精细图案中互连冗余部分而不是通过检查识别的缺陷部分。