中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

259 records (took 0.026 seconds)

    Method of manufacturing semiconductor device
    51.
    发明授权
    Method of manufacturing semiconductor device 有权

    公开(公告)号：US07989295B2

    公开(公告)日：2011-08-02

    申请号：US13014190

    申请日：2011-01-26

    Applicant: Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

    Inventor： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

    IPC: H01L21/336

    CPC classification number: H01L29/7828 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068

    Abstract: A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.

    Semiconductor device
    53.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07902555B2

    公开(公告)日：2011-03-08

    申请号：US12325377

    申请日：2008-12-01

    Applicant: Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

    Inventor： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

    IPC: H01L29/15 ,  H01L31/0312

    CPC classification number: H01L29/0847 ,  H01L29/0623 ,  H01L29/0642 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/7828

    Abstract: A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved at the time of interruption, and at the same time, the generation of the hot spot where in a specific portion is prevented at the time of conduction to suppress deterioration in a specific portion, thereby ensuring a long-term reliability. Further, when the semiconductor chip is used in an L load circuit or the like, for example, at the time of conduction or during a transient response time to the interrupted state, in an index such as a short resistant load amount and an avalanche resistant amount, which are indexes of a breakdown tolerance when overcurrent or overvoltage occurs, the current concentration on a specific portion can be prevented, and thus, these breakdown tolerances can also be improved.

    Abstract translation: 作为将反向偏置电流保持集中在凸角上的电流 - 浓度释放区域的异质半导体角区域设置在异质半导体区域中。 由此，可以防止凸角上的电流集中。 结果，在中断时可以提高中断性能，同时，在导通时防止特定部位的热点的产生，抑制特定部分的劣化，从而确保 长期可靠。 此外，例如在导通时或半导体芯片用于L负载电路等时，例如，在短时间响应时间到中断状态时，以诸如短路负载量和雪崩阻抗的指标 量是当发生过电流或过电压时的击穿容限的指标，可以防止特定部分上的电流浓度，因此也可以提高这些击穿公差。

    Method for forming electrode for battery
    54.
    发明授权
    Method for forming electrode for battery 有权
    电池用电极形成方法

    公开(公告)号：US07901738B2

    公开(公告)日：2011-03-08

    申请号：US11700132

    申请日：2007-01-31

    Applicant: Tetsuya Hayashi

    Inventor： Tetsuya Hayashi

    IPC: B05D5/12 ,  B05D1/28

    CPC classification number: H01M4/0404 ,  H01M2/1673

    Abstract: A method for forming an electrode for a battery includes the step of forming a porous layer on the surface of an electrode hoop formed at its surface with a mixture layer containing an active material. The porous layer is formed in the following manner: A gravure roll is rotated oppositely to the direction of movement of the electrode hoop while being allowed to abut against the surface of the moving electrode hoop, thereby applying a coating fluid serving as a precursor of the porous layer to the surface of the electrode hoop. A plurality of grooves formed in the circumferential surface of the gravure roll extend in parallel in oblique directions against the rotation direction of the gravure roll from the central line of the circumferential surface to the outer edges of the circumferential surface so as to be arranged in a symmetrical manner relative to the central line.

    Abstract translation: 形成电池用电极的方法包括在其表面形成的电极环的表面上形成多孔层的步骤，该混合层含有活性物质。 以下述方式形成多孔层：使凹版辊与电极环的移动方向相反地旋转，同时抵靠移动电极环的表面，从而涂布作为 多孔层到电极环的表面。 形成在凹版滚筒的圆周表面中的多个凹槽相对于凹版辊的旋转方向在倾斜方向上从圆周表面的中心线延伸到圆周表面的外边缘，以便布置在 对称的方式相对于中心线。

    Electrostatic discharge protection circuit and semiconductor device
    55.
    发明授权
    Electrostatic discharge protection circuit and semiconductor device 有权
    静电放电保护电路和半导体器件

    公开(公告)号：US07852608B2

    公开(公告)日：2010-12-14

    申请号：US11882865

    申请日：2007-08-06

    Applicant: Masanori Yoshitani ,  Tetsuya Hayashi ,  Tomokazu Higuchi

    Inventor： Masanori Yoshitani ,  Tetsuya Hayashi ,  Tomokazu Higuchi

    IPC: H02H9/04

    CPC classification number: H03K17/08122 ,  H01L27/0251 ,  H03K17/6872

    Abstract: An electrostatic discharge protection circuit and a semiconductor device that prevent the breakdown of a semiconductor device caused by an electrostatic discharge (ESD) which suddenly changes. When voltage which is far higher than VDD1 is applied to a power supply line as a result of an ESD, a great electric potential difference is produced between VDD1 and VSS. At this time an electric current path for making an electric charge generated by overvoltage flow to a grounding line is formed by a clamp circuit. As a result, an electric current flows into GND of a circuit block. This prevents the production of a great electric potential difference between VDD1 and VSS. In addition, at this time a rapid change in the level of the overvoltage applied to a signal line is suppressed by a protection circuit. This prevents the dielectric breakdown of gate oxide films of transistors included in a circuit block which receives a control signal.

    Abstract translation: 一种防止由突然变化的静电放电（ESD）引起的半导体器件击穿的静电放电保护电路和半导体器件。 当远高于VDD1的电压作为ESD施加到电源线时，在VDD1和VSS之间产生大的电位差。 此时，通过钳位电路形成用于使由过电压产生的电荷流向接地线的电流路径。 结果，电流流入电路块的GND。 这样可以防止在VDD1和VSS之间产生很大的电位差。 此外，此时，通过保护电路来抑制施加到信号线的过电压的电平的急剧变化。 这防止包含在接收控制信号的电路块中的晶体管的栅极氧化膜的介电击穿。

    Lithium ion secondary battery and method for producing the same
    56.
    发明授权
    Lithium ion secondary battery and method for producing the same 有权
    锂离子二次电池及其制造方法

    公开(公告)号：US07816038B2

    公开(公告)日：2010-10-19

    申请号：US11578964

    申请日：2005-04-19

    Applicant: Tsumoru Ohata ,  Junji Nakajima ,  Tetsuya Hayashi ,  Shigeo Ikuta ,  Akiko Fujino ,  Eitaro Nakamura

    Inventor： Tsumoru Ohata ,  Junji Nakajima ,  Tetsuya Hayashi ,  Shigeo Ikuta ,  Akiko Fujino ,  Eitaro Nakamura

    IPC: H01M4/04 ,  H01M4/62

    CPC classification number: H01M10/0567 ,  H01M4/0402 ,  H01M4/13 ,  H01M4/131 ,  H01M4/133 ,  H01M4/139 ,  H01M4/62 ,  H01M10/0525 ,  H01M2300/004 ,  Y10T29/49115

    Abstract: A method for producing a lithium ion secondary battery includes the steps of: forming a positive electrode mixture layer on a positive electrode substrate to obtain a positive electrode; forming a negative electrode mixture layer on a negative electrode substrate to obtain a negative electrode; forming an electronically insulating porous film that is bonded to a surface of at least one of the positive electrode and the negative electrode; interposing a separator between the positive electrode and the negative electrode to form an electrode plate assembly; and impregnating the electrode plate assembly with a non-aqueous electrolyte. The step of forming a porous film includes the steps of: preparing a porous film paste that contains a film binder comprising a thermo-cross-linkable resin and a particulate filler; and applying the porous film paste onto a surface of at least one of the positive electrode and the negative electrode and heating the resultant applied film.

    Abstract translation: 锂离子二次电池的制造方法包括以下步骤：在正极基板上形成正极合剂层，得到正极; 在负极基板上形成负极合剂层，得到负极; 形成与所述正极和所述负极中的至少一个的表面接合的电子绝缘性多孔膜， 在正极和负极之间插入隔板以形成电极板组件; 并用非水电解质浸渍电极板组件。 形成多孔膜的步骤包括以下步骤：制备含有包含可热交联树脂和颗粒填料的膜粘合剂的多孔膜糊; 以及将所述多孔膜浆料涂布在所述正极和负极中的至少一个的表面上，并加热所得到的涂膜。

    Semiconductor device and method of producing the same
    57.
    发明授权
    Semiconductor device and method of producing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07671383B2

    公开(公告)日：2010-03-02

    申请号：US11714214

    申请日：2007-03-06

    Applicant: Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

    Inventor： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

    IPC: H01L29/732

    CPC classification number: H01L29/267 ,  H01L21/0475 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7828

    Abstract: A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.

    Abstract translation: 一种半导体器件，包括：具有主面的第一导电型半导体基底; 与半导体基板的主面接触并与半导体基底结合形成异质结的异质半导体区域，半导体基底和异质半导体区域组合形成连接端部; 限定与半导体基底接触并具有厚度的接合面的栅极绝缘膜; 以及栅电极，其经由所述栅极绝缘膜与所述接合端部相邻设置，并且在远离所述接合端部的位置中以最短间隔限定最短点，从所述最短点到接触点相对于所述接合端垂直延伸的线 接合面在接触点和接合端部之间形成的距离小于与半导体基底接触的栅极绝缘膜的厚度。

    Method of manufacturing semiconductor device
    60.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07531396B2

    公开(公告)日：2009-05-12

    申请号：US11374418

    申请日：2006-03-14

    Applicant: Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

    Inventor： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

    IPC: H01L21/338 ,  H01L21/066

    CPC classification number: H01L29/66068 ,  H01L21/8213 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7828

    Abstract: A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different from that of the semiconductor body, and a gate electrode formed in a junction portion between the hetero semiconductor region and the semiconductor body through a gate insulating film. The method includes a first process of forming a predetermined trench by using a mask layer having a predetermined opening on one main surface side of the semiconductor body, a second process of forming a buried region adjacent to at least a side wall of the trench and so as to extend from the trench, a third process of forming a hetero semiconductor layer so as to adjoin the semiconductor body and the buried region, and a fourth process of forming the hetero semiconductor region by patterning the hetero semiconductor layer.

    Abstract translation: 公开了制造半导体器件的方法。 半导体器件包括第一导电类型的半导体本体，与半导体本体的一个主表面相邻且具有与半导体本体不同的带隙的异质半导体区域，以及形成在该半导体器件之间的接合部分中的栅电极 异质半导体区域和半导体本体通过栅极绝缘膜。 该方法包括通过使用在半导体主体的一个主表面侧上具有预定开口的掩模层来形成预定沟槽的第一工艺，形成与沟槽的至少侧壁相邻的掩埋区域的第二工艺 从沟槽延伸，形成与半导体本体和掩埋区相邻的异质半导体层的第三工序，以及通过图案化杂半导体层形成异质半导体区的第四工序。

Patent Agency Ranking