公开(公告)号：US08175143B1

公开(公告)日：2012-05-08

申请号：US12037284

申请日：2008-02-26

Applicant: Wilson Wong ,  Tin H. Lai ,  Allen Chan ,  Tim Tri Hoang ,  Sergey Shumarayev

Inventor： Wilson Wong ,  Tin H. Lai ,  Allen Chan ,  Tim Tri Hoang ,  Sergey Shumarayev

IPC: H03H7/30

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03745 ,  H04L2025/03783

Abstract: A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.

Abstract translation: 用于在自适应均衡中选择正确的均衡曲线的方法和电路使用反馈回路，其中输入的高速串行数据被数字化和反序列化以用于设备的其余部分，并且还被自适应状态机 以提取用于数字化的参考电平并控制均衡曲线。 参考电平的检测和均衡曲线的选择可以以不同的速率进行，以避免彼此干扰。 状态机优选是可编程的。 这在任何设备中是有用的，但是特别适用于诸如PLD或其他可编程集成电路设备的可编程设备，其中条件可以根据用户逻辑设计而变化。

公开(公告)号：US08127215B2

公开(公告)日：2012-02-28

申请号：US13151717

申请日：2011-06-02

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H03M13/03

CPC classification number: H04L25/45

Abstract: A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

Abstract translation: 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US07920621B2

公开(公告)日：2011-04-05

申请号：US11522284

申请日：2006-09-14

Applicant: Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

Inventor： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC: H03H7/30

CPC classification number: H04L25/03885

Abstract: Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

Abstract translation: 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

公开(公告)号：US07659745B1

公开(公告)日：2010-02-09

申请号：US12218688

申请日：2008-07-16

Applicant: Wilson Wong ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Wilson Wong ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H03K19/0175 ,  H03K5/00 ,  G06F7/38

CPC classification number: H03K19/17744

Abstract: A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.

Abstract translation: 可编程逻辑器件（“PLD”）包括用于在几个方面中的任何一个中可选地且可变地修改输入信号的特性的电路。 这样的修改的示例包括将信号AC耦合到PLD中，对信号进行低通滤波（具有可选择的低通滤波器转角频率），移位输入信号的公共电压，和/或使输入信号经受可选择量的 衰减。

公开(公告)号：US07495517B1

公开(公告)日：2009-02-24

申请号：US11610892

申请日：2006-12-14

Applicant: Tim Tri Hoang ,  Sergey Shumarayev

Inventor： Tim Tri Hoang ,  Sergey Shumarayev

IPC: H03L7/06 ,  H03L7/093 ,  H03L7/095 ,  H03L7/099 ,  H03L7/18

CPC classification number: H03L7/18 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/095 ,  H03L7/099 ,  Y10S331/02

Abstract: Techniques are provided for dynamically adjusting the frequency range of phase-locked loops (PLLs). Phase detection circuitry in a PLL generates a control signal in response to a periodic input signal and a feedback signal. When the control signal deviates outside a valid range, the input frequency range of the PLL is dynamically adjusted to include the periodic input signal frequency. The input frequency range of the PLL is adjusted by changing one or more frequency ratios in the PLL. The resistance and/or capacitance of a loop filter in the PLL can be dynamically adjusted to control the bandwidth of the PLL.

Abstract translation: 提供了用于动态调整锁相环（PLL）频率范围的技术。 PLL中的相位检测电路响应于周期性输入信号和反馈信号产生控制信号。 当控制信号偏离有效范围时，PLL的输入频率范围被动态地调整为包括周期性输入信号频率。 通过改变PLL中的一个或多个频率比来调整PLL的输入频率范围。 可以动态地调整PLL中的环路滤波器的电阻和/或电容，以控制PLL的带宽。

公开(公告)号：US07417462B1

公开(公告)日：2008-08-26

申请号：US11726174

申请日：2007-03-20

Applicant: Wilson Wong ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Wilson Wong ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H03K19/0175 ,  H03K5/00 ,  G06F7/38

CPC classification number: H03K19/17744

Abstract: A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.

Abstract translation: 可编程逻辑器件（“PLD”）包括用于在几个方面中的任何一个中可选地且可变地修改输入信号的特性的电路。 这样的修改的示例包括将信号AC耦合到PLD中，对信号进行低通滤波（具有可选择的低通滤波器转角频率），移位输入信号的公共电压，和/或使输入信号经受可选择量的 衰减。

公开(公告)号：US08744012B1

公开(公告)日：2014-06-03

申请号：US13369108

申请日：2012-02-08

Applicant: Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

Inventor： Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

IPC: H03K9/00

CPC classification number: H04L1/203 ,  G01R31/31711

Abstract: System, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with a serial input signal either during or after equalization. The device may include an equalizer and eye viewer circuitry configured to select a node of the equalizer for eye monitoring of the input signal, which may be during or after equalization. In one embodiment, the eye viewer circuitry may provide a separate sampler for each respective node, while sharing a control logic and phase interpolator among the samplers. The eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the serial input signal, as seen from the selected node of the equalizer.

Abstract translation: 提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和设备。 例如，集成电路器件的一个实施例可能能够在均衡期间或之后确定与串行输入信号相关联的眼图。 该装置可以包括均衡器和眼睛观察器电路，其被配置为选择均衡器的节点，用于在均衡期间或之后的输入信号的眼睛监视。 在一个实施例中，眼睛观察器电路可以为每个相应节点提供单独的采样器，同时在采样器之间共享控制逻辑和相位插值器。 从均衡器的选定节点看，眼睛观察器电路可以确定与串行输入信号相关联的眼图的水平和垂直边界。

公开(公告)号：US08626474B2

公开(公告)日：2014-01-07

申请号：US12762848

申请日：2010-04-19

Applicant: Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

Inventor： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC: G06F7/60 ,  G06G7/62 ,  G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

公开(公告)号：US08542042B1

公开(公告)日：2013-09-24

申请号：US13532528

申请日：2012-06-25

Applicant: Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff

Inventor： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff

IPC: H03L7/06

CPC classification number: H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

Abstract: One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及一种可断裂的PLL电路。 断裂PLL电路包括产生第一频率输出的第一锁相环电路，第二锁相环电路; 布置成产生第二频率输出和多个共享输出资源。 可重构电路被布置成使得第一和第二频率输出中的任一个可由多个共享输出资源中的每一个接收。 另一实施例涉及一种集成电路，其包括多个PMA模块，多个多用途PLL电路和可编程时钟网络。 可编程时钟网络被布置为允许由多用途PLL电路输出的时钟信号被PMA模块选择性地用于收发器应用或由用于非收发器应用的其它电路。 还公开了其它实施例和特征。

公开(公告)号：US08504882B2

公开(公告)日：2013-08-06

申请号：US12884305

申请日：2010-09-17

Applicant: Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

Inventor： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

IPC: G06F11/00

CPC classification number: G06F11/267

Abstract: An integrated circuit (“IC”) includes circuitry for use in testing a serial data signal. One such IC includes circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. One such IC also includes circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. Such an IC provides output signals indicative of results of its operations. One such IC operates in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract translation: 集成电路（“IC”）包括用于测试串行数据信号的电路。 一个这样的IC包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。 一个这样的IC还包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 这样的IC提供指示其操作结果的输出信号。 一个这样的IC以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。