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    DYNAMIC ADDRESS TRANSLATION WITH LOAD REAL ADDRESS
    51.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH LOAD REAL ADDRESS 失效
    动态地址翻译与负载实地址

    公开(公告)号：US20090182973A1

    公开(公告)日：2009-07-16

    申请号：US11972705

    申请日：2008-01-11

    申请人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F9/34

    CPC分类号： G06F12/1009 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/34 ,  G06F9/342 ,  G06F2212/651 ,  G06F2212/657

    摘要： What is provided is a load real address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction containing an opcode is obtained indicating that a load real address is to be performed. The instruction further identifies a first general register. Based on the contents of the machine instruction, a virtual address to be translated is obtained. Dynamic address translation is performed on the virtual address to obtain a segment-frame absolute address of a large block of data in memory. If an extended DAT facility and a format control field in the segment table entry are enabled, the address of the block of data is saved in the first general register. A page index portion and a byte index portion of the virtual address may also be saved in the first general register.

    摘要翻译： 提供了为计算机系统的机器结构定义的负载实地址功能。 在一个实施例中，获得包含操作码的机器指令，指示要执行负载实际地址。 该指令进一步标识第一个通用寄存器。 根据机器指令的内容，获得要翻译的虚拟地址。 对虚拟地址执行动态地址转换，以获得存储器中大块数据的段帧绝对地址。 如果分段表项中的扩展DAT功能和格式控制字段被使能，数据块的地址将保存在第一个通用寄存器中。 虚拟地址的页索引部分和字节索引部分也可以保存在第一通用寄存器中。

    Method and apparatus for enabling an interpretive execution subset
    52.
    发明授权
    Method and apparatus for enabling an interpretive execution subset 失效
    用于启用解释执行子集的方法和装置

    公开(公告)号：US5317754A

    公开(公告)日：1994-05-31

    申请号：US602029

    申请日：1990-10-23

    申请人： Geoffrey O. Blandy ,  Lisa C. Heller ,  Robert E. Murray

    发明人： Geoffrey O. Blandy ,  Lisa C. Heller ,  Robert E. Murray

    IPC分类号： G06F9/48 ,  G06F12/10 ,  G06F9/46

    CPC分类号： G06F9/4843 ,  G06F12/1036

    摘要： An apparatus and method are established for recognizing guest virtual machines which require only a subset of interpretive execution facilities. The interpretive execution initialization process recognizes subset candidates and bypasses initialization of those facilities not required by the candidates. The candidates are typically short duration jobs and a reduction of initialization and termination overhead creates a substantial performance improvement. The translation lookaside buffer operation is modified to flag subset guest entries as host entries and to associate a unique segment table origin with each subset guest. This allows the TLB entries to remain between guest machine dispatches eliminating TLB purge time and allowing potential reuse of TLB entries if the same guest is repeatedly dispatched within a short time period. The guest machine state description is modified to flag subset candidates based on address translation and timing requirements. Initialization of timing facilities is bypassed in certain subset modes further reducing initialization overhead.

    摘要翻译： 建立了一种用于识别仅需要解释性执行设施的子集的客体虚拟机的装置和方法。 解释执行初始化过程识别子集候选者，并绕过候选人不需要的这些设施的初始化。 候选人通常是短期工作，并且初始化和终止开销的减少创造了显着的性能改进。 修改翻译后备缓冲区操作被修改为将子组客户条目标记为主机条目，并将唯一段表原点与每个子组客户关联。 这允许TLB条目保留在客机调度之间，消除TLB清除时间，并允许在短时间内重复发送同一客户端的TLB条目的潜在重用。 根据地址转换和时序要求修改访客机状态描述以标记子集候选。 定时设备的初始化在某些子集模式中被绕过，从而进一步降低了初始化开销。

    Method and apparatus to limit millicode routine end branch prediction
    53.
    发明授权
    Method and apparatus to limit millicode routine end branch prediction 有权
    终止分支预测的方法和装置

    公开(公告)号：US09086886B2

    公开(公告)日：2015-07-21

    申请号：US12821690

    申请日：2010-06-23

    申请人： Brian R. Prasky ,  James J. Bonanno ,  Lisa C. Heller

    发明人： Brian R. Prasky ,  James J. Bonanno ,  Lisa C. Heller

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3806 ,  G06F9/3017

    摘要： A computing system method, program and hardware for correlation of millicode predictions with specific millicode routines receives architected millicode and stores the millicode in internal memory. The computer systems processors' pipeline is employed to predict and select a branch target buffer's (BTB) target address. A computer millicode control enabling an operating system (O/S) multi-task control between multiple user programs able to use millicode routines and ensuring that the programs do not interfere with each other, by use of a branch target buffer (BTB) prediction of a branch target to ensure that a millicode routine does not fetch outside of said millicode routine while performing operations as required by said millicode routing, said branch target buffer prediction employing a correlation mechanism for predicting millicoded branch millicode entry and millicode end instructions and for correlating millicode end predictions with specific millicode routines.

    摘要翻译： 一个计算系统方法，程序和硬件相关的millicode预测与特定的millicode例程接收架构式的代码，并将millicode存储在内部存储器中。 计算机系统处理器的流水线用于预测和选择分支目标缓冲器（BTB）目标地址。 一种计算机微码控制，其使得能够使用毫秒代码程序的多个用户程序之间的操作系统（O / S）多任务控制，并且通过使用分支目标缓冲器（BTB）预测来确保程序不相互干扰 分支目标，以确保毫秒代码程序在执行所述毫代码路由所要求的操作之前不会从所述毫代码程序外部获取，所述分支目标缓冲器预测采用用于预测毫米编码的分支毫代数条目和毫分节结束指令的相关机制，并且用于关联millicode 用特定的millicode例程结束预测。

    Diagnose instruction for serializing processing
    54.
    发明授权
    Diagnose instruction for serializing processing 有权

    公开(公告)号：US08595469B2

    公开(公告)日：2013-11-26

    申请号：US12822886

    申请日：2010-06-24

    申请人： Lisa C. Heller

    发明人： Lisa C. Heller

    IPC分类号： G06F9/00

    CPC分类号： G06F9/30087 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30185 ,  G06F9/45533 ,  G06F9/52

    摘要： A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock.

    Perform frame management function instruction for clearing blocks of main storage
    57.
    发明授权
    Perform frame management function instruction for clearing blocks of main storage 有权
    执行清理主存储块的帧管理功能指令

    公开(公告)号：US08335906B2

    公开(公告)日：2012-12-18

    申请号：US11972718

    申请日：2008-01-11

    申请人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1036 ,  G06F9/30043 ,  G06F9/30145

    摘要： What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained containing an opcode for a frame management instruction identifying a first and second general register. Clear frame information is obtained from the first general register having a frame size field indicating whether a storage frame is a small or large block of data. The second general register contains an operand address of a storage frame. If the storage frame is a small block, all bytes of the small block of data are set to zero. If the storage frame is a large block of data, an operand address of an initial first block of data within the large block is obtained from the second general register. All data of all blocks within the large block are cleared starting from the initial first block.

    摘要翻译： 公开的是针对计算机系统的机器结构定义的帧管理功能。 在一个实施例中，获得包含识别第一和第二通用寄存器的帧管理指令的操作码的机器指令。 从具有指示存储帧是小数据块还是大数据块的帧大小字段的第一通用寄存器获得清除帧信息。 第二个通用寄存器包含存储帧的操作数地址。 如果存储帧是小块，则小块数据的所有字节都被设置为零。 如果存储帧是大数据块，则从第二通用寄存器获得大块内的初始第一数据块的操作数地址。 大块内的所有块的所有数据从初始第一块开始清零。