摘要:
A pipelined analog-to-digital converter (ADC) is calibrated to enable production of an n-bit digital output representing an n-2 bit binary word, where “n” is a selected large positive integer, for example without limitation on the order of ten (10). In an analog-to-digital converter (ADC) having a plurality stages, each stage includes a stage input connection, a stage output connection, and a capacitor circuit including first and second predetermined capacitors (C1 and C2) and a variable capacitance calibration capacitor (Ccal). The first and second capacitors and the variable capacitance calibration capacitor are connected to each other at a capacitor common node. An amplifier input connection is connected to a capacitor common node. A comparator input connection (CIC) is connected to a stage input connection. A track and hold circuit (THC) is coupled to an amplifier output connection, and a source follower circuit (SF) is connected to a stage output connection.
摘要:
The synthesis of high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock by using a shift register. The shift register may be clocked by another clock signal at a higher frequency than the divided version of the VCO output clock. The phase differences between the plurality of phase shifted signals and a divided version of a reference clock may then be detected and converted to the analog control signals.
摘要:
A communication system is provided which draws virtually no loop current during a ringing burst and only draws on-hook loop current during the caller ID field. More particularly, ringer burst circuitry may be powered from the user powered circuitry by the transmission of power across the isolation barrier rather than being powered from the phone line. Thus, loop current need not be drawn from the TIP/RING lines during ringer bursts. The isolation barrier may be a capacitive isolation barrier which allows bidirectional communication and extraction of power from signals transmitted across the barrier.
摘要:
Transconductance amplifiers having high speed, a wide output voltage swing, good linearity and expandability are disclosed. All active devices are n-channel MOSFET devices with the output current of the amplifiers being provided by devices with their sources tied to ground. Connection of one of the MOSFET transconductance amplifiers to a MOSFET load device and appropriate control of the MOSFET resistance devices in the transconductance amplifier and the load circuit provides a variable gain amplifier having a good estimation of an exponential response to the gain control signal, thus being suitable for use in closed loop automatic gain control circuits.
摘要:
A delta sigma modulator provides dual phase sampling of analog input and/or a reference voltage. This dual phase sampling may be realized using a switched capacitor circuit having dual legs with a capacitor on each such leg. The dual phase sampling of the reference voltage poses a complication that mandates the necessity of providing a compensation signal. The delta sigma modulator is provided with appropriate circuitry to provide a compensation signal that compensates for the reduced signal level due to the dual sampling. In particular, the delta sigma modulator compensates for the reduced level of the output from an integrating amplifier circuit due to the timing necessary to implement the dual sampling approach.
摘要:
An improved bias generator provides a bias voltage output which is a function of an input current Iprog and provides a bias current to a preselected load which tracks the input signal independently of temperature. The amount the bias voltage output changes with temperature is determined by (1) V(T, Iprog), a voltage-current temperature dependent function of the base-emitter voltage drop of at least one transistor and (2) X, a scalar which is easily provided by setting the ratio of two resistors. The generator can therefore be easily constructed for particular circuit loads which include at least one semiconductive junction such that the biasing current through the load will be substantially independent of temperature.
摘要:
An improved current mode operational rectifier having loop transmissions through both feedback paths of an operational amplifier stage which limit at unity gain. An improved bias generator which can be used to bias the operational rectifier is also disclosed.
摘要:
An improved bias generator provides a bias voltage output which varies with temperature in accordance with a predetermined voltage-temperature function.
摘要:
A controller for a capacitive touch screen or the like includes a touch resolve subsystem and a processor. The touch resolve subsystem, when activated, measures a plurality of capacitance values using a plurality of input pins. The processor uses the plurality of capacitance values at each of a plurality of values of a parameter to create an interference map.
摘要:
A controller for a capacitive touch screen includes a touch resolve subsystem and a processor. The touch resolve subsystem, in response to a trigger input, measures a plurality of capacitance values using a plurality of input pins. The processor controls the touch resolve subsystem to acquire a baseline capacitance in a calibration mode, to acquire a frame comprising the plurality of capacitance values in a normal operation mode, and to update the baseline capacitance to a new baseline capacitance in the normal operation mode in response to the frame without entering the calibration mode.