公开(公告)号：US08772107B2

公开(公告)日：2014-07-08

申请号：US14033886

申请日：2013-09-23

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L21/336

CPC分类号： H01L29/42328 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7889

摘要： A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate.

摘要翻译： 包括在非易失性半导体存储器中的非易失性半导体存储晶体管包括从基板侧依次形成的源极区，沟道区和漏极区的岛状半导体，中空柱状浮栅配置成 以沟道绝缘膜插入在浮动栅极和沟道区域之间的方式围绕沟道区域的外周，并且以这样的方式围绕浮动栅极的外周布置的中空柱状控制栅极 多晶硅间绝缘膜介于控制栅极和浮栅之间的方式。 多晶硅间绝缘膜被布置成位于控制栅极的浮动栅极和上，下和内侧表面之间。

公开(公告)号：US08759178B2

公开(公告)日：2014-06-24

申请号：US13666445

申请日：2012-11-01

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L21/26513 ,  H01L21/3081 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/78

摘要： A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.

摘要翻译： 制造方法包括在硅衬底上形成鳍状硅层，在鳍状硅层周围形成第一绝缘膜，在鳍状硅层上形成柱状硅层; 在柱状硅层的上部形成扩散层，鳍状硅层的上部和柱状硅层的下部， 形成栅极绝缘膜，多晶硅栅极电极和多晶硅栅极布线; 在鳍状硅层的上部的扩散层的上部形成硅化物; 沉积层间绝缘膜，暴露多晶硅栅电极和多晶硅栅极布线，蚀刻多晶硅栅电极和多晶硅栅极布线，然后沉积金属以形成金属栅极电极和金属栅极布线; 并形成接触。

公开(公告)号：US08697511B2

公开(公告)日：2014-04-15

申请号：US13891655

申请日：2013-05-10

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78642 ,  H01L29/78651 ,  H01L29/78654

摘要： A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact.

公开(公告)号：US08664063B2

公开(公告)日：2014-03-04

申请号：US13690308

申请日：2012-11-30

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/66666

摘要： A method for producing a semiconductor device includes the steps of forming a planar silicon layer, first and second pillar-shaped silicon layers on a silicon substrate; forming a gate insulating film, depositing a metal film and a polysilicon around the gate insulating film, conducting planarization, conducting etching to expose upper portions of the first and second pillar-shaped silicon layers, forming first and second insulating film sidewalls, and forming first and second gate electrodes and a gate line; forming n-type diffusion layers in upper and lower portions of the first pillar-shaped silicon layer, and forming p-type diffusion layers in upper and lower portions of the second pillar-shaped silicon layer; forming a third insulating film sidewall on side walls of the first and second insulating film sidewalls, the first and second gate electrodes, and the gate line; and forming a silicide.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在硅衬底上形成平面硅层，第一和第二柱状硅层; 形成栅极绝缘膜，在栅绝缘膜周围沉积金属膜和多晶硅，进行平面化，导电蚀刻以暴露第一和第二柱状硅层的上部，形成第一和第二绝缘膜侧壁，并形成第一 和第二栅电极和栅极线; 在第一柱状硅层的上部和下部形成n型扩散层，在第二柱状硅层的上部和下部形成p型扩散层; 在第一和第二绝缘膜侧壁，第一和第二栅极电极和栅极线的侧壁上形成第三绝缘膜侧壁; 并形成硅化物。

公开(公告)号：US10937902B2

公开(公告)日：2021-03-02

申请号：US15968991

申请日：2018-05-02

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/78 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/423

摘要： A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.

公开(公告)号：US10923591B2

公开(公告)日：2021-02-16

申请号：US16587728

申请日：2019-09-30

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088

摘要： A method for producing an SGT employs a gate-last process that includes forming a fin-shaped semiconductor layer, a pillar-shaped semiconductor layer, a gate electrode, and a gate line by self-alignment. The gate line and the pillar-shaped semiconductor layer are formed in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends.

公开(公告)号：US10483376B1

公开(公告)日：2019-11-19

申请号：US16520892

申请日：2019-07-24

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Nozomu Harada

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/06

摘要： A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.

公开(公告)号：US10475922B2

公开(公告)日：2019-11-12

申请号：US15800913

申请日：2017-11-01

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L21/768

摘要： A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and a first insulating film around the fin-shaped semiconductor layer. A first contact is on the fin-shaped semiconductor layer, where the first contact is metal contact. A first gate insulating film is around the first contact and a fourth contact on the first contact, and a second gate insulating film is around the fourth contact.

公开(公告)号：US10453941B2

公开(公告)日：2019-10-22

申请号：US15849026

申请日：2017-12-20

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Nozomu Harada

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/06

摘要： A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.

公开(公告)号：US10396197B2

公开(公告)日：2019-08-27

申请号：US15858176

申请日：2017-12-29

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

摘要： A semiconductor device includes a planar semiconductor layer formed on a substrate; a pillar-shaped semiconductor layer formed on the planar semiconductor layer; a gate insulating film surrounding the pillar-shaped semiconductor layer; a first metal surrounding the gate insulating film, the first metal being in contact with an upper portion of the planar semiconductor layer; a gate formed above the first metal so as to surround the gate insulating film, the gate being electrically insulated from the first metal; and a second metal formed above the gate so as to surround the gate insulating film, the second metal being electrically insulated from the gate, the second metal having an upper portion electrically connected to an upper portion of the pillar-shaped semiconductor layer.