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公开(公告)号：US20130292775A1
公开(公告)日：2013-11-07
申请号：US13936214
申请日：2013-07-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Guang-Yaw Hwang , Ling-Chun Chou , I-Chang Wang , Shin-Chuan Huang , Jiunn-Hsiung Liao , Shin-Chi Chen , Pau-Chung Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chieh-Te Chen
IPC: H01L27/088
CPC classification number: H01L27/088 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66636 , H01L29/7848
Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.
Abstract translation: 应变硅衬底结构包括设置在衬底上的第一晶体管和第二晶体管。 第一晶体管包括第一栅极结构和设置在第一栅极结构的两侧的两个第一源极/漏极区域。 第一源极/漏极到栅极间距在每个第一源极/漏极区域和第一栅极结构之间。 第二晶体管包括第二栅极结构和设置在第二栅极结构的两侧的两个源极/漏极掺杂区域。 第二源极/漏极到栅极间距在每个第二源极/漏极区域和第二栅极结构之间。 第一源极/漏极到栅极距离小于第二源极/漏极到栅极距离。
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公开(公告)号：US11107879B2
公开(公告)日：2021-08-31
申请号：US16154680
申请日：2018-10-08
Inventor： Kai-Lou Huang , Fu-Che Lee , Feng-Yi Chang , Chieh-Te Chen , Meng-Chia Tsai
IPC: H01L27/108 , H01L49/02 , H01L23/532
Abstract: A capacitor structure includes a substrate having thereon a storage node contact, a cylinder-shaped bottom electrode disposed on the storage node contact, a supporting structure horizontally supporting a sidewall of the cylinder-shaped bottom electrode, a capacitor dielectric layer conformally covering the cylinder-shaped bottom electrode and the supporting structure, and a top electrode covering the capacitor dielectric layer. The supporting structure has a top surface that is higher than that of the cylinder-shaped bottom electrode. The top surface of the supporting structure has a V-shaped sectional profile.
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公开(公告)号：US10593677B2
公开(公告)日：2020-03-17
申请号：US15947856
申请日：2018-04-08
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen , Yi-Ching Chang
IPC: H01L27/108 , H01L21/8242 , H01L23/532 , H01L21/768 , H01L23/528
Abstract: The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor structure with capacitor landing pad includes a substrate having a plurality of contact structures, a first dielectric layer disposed on the substrate and the contact structures, and a plurality of capacitor landing pads, each of the capacitor landing pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the capacitor landing pads presents a shape of a wide top and a narrow bottom and a top surface of the capacitor landing pads have a concave shape.
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公开(公告)号：US20200020524A1
公开(公告)日：2020-01-16
申请号：US16039284
申请日：2018-07-18
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen , Ching-Pin Hsu
IPC: H01L21/02 , H01L21/3065 , H01L21/67 , H01L21/3213
Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.
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55.发明授权公开(公告)号：US10256312B1
公开(公告)日：2019-04-09
申请号：US15886812
申请日：2018-02-01
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen , Yi-Ching Chang
IPC: H01L29/423 , H01L21/768 , H01L23/528 , H01L29/66 , H01L23/522 , H01L23/532 , H01L23/00 , H01L23/31
Abstract: A semiconductor structure includes a contact plug located on a barrier layer in a contact hole; a first conductive feature integrally formed with the contact plug on the barrier layer; a second conductive feature disposed on the interlayer dielectric layer; and a gap between the first and second conductive features. The gap includes a vertical trench recessed into the interlayer dielectric layer, and a discontinuity in the barrier layer. The discontinuity extends below the second conductive feature to form an undercut structure.
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Patent Agency Ranking
公开(公告)号：US10249629B1
公开(公告)日：2019-04-02
申请号：US15876220
申请日：2018-01-22
Inventor： Li-Chiang Chen , Fu-Che Lee , Ming-Feng Kuo , Chieh-Te Chen , Hsien-Shih Chu
IPC: H01L27/108 , H01L21/311 , H01L29/06 , H01L29/423 , H01L21/306 , H01L21/308 , H01L21/027 , H01L21/768 , H01L21/3105 , H01L21/3213
Abstract: The present invention provides a method for forming buried word lines. Firstly, a substrate is provided, having a plurality of shallow trench isolations disposed therein, next, a plurality of first patterned material layers are formed on the substrate, a plurality of first recesses are disposed between every two adjacent first patterned material layers, a second patterned material layer is formed in the first recesses, and using the first patterned material layers and the second patterned material layer as the protect layers, and a first etching process is then performed, to form a plurality of second recesses in the substrate.
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公开(公告)号：US20190057967A1
公开(公告)日：2019-02-21
申请号：US16027267
申请日：2018-07-04
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L27/108 , G11C11/404 , G11C11/4074 , G11C7/02 , H01L49/02
CPC classification number: H01L27/10814 , G11C7/02 , G11C11/404 , G11C11/4074 , H01L27/10823 , H01L27/10852 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10897 , H01L28/90
Abstract: A semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.
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公开(公告)号：US20180374702A1
公开(公告)日：2018-12-27
申请号：US15660967
申请日：2017-07-27
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen , Yi-Ching Chang
IPC: H01L21/033 , H01L21/3213
CPC classification number: H01L21/0337 , H01L21/0332 , H01L21/32139 , H01L27/10894
Abstract: A method of forming a semiconductor device includes the following steps. First of all, a material layer is formed on a substrate, and a sidewall image transferring process is performed to form plural first mask patterns on the material layer, with the first mask patterns parallel extended along a first direction. Next, a pattern splitting process is performed to remove a portion of the first mask patterns to form plural second openings, with the second openings parallel extended along a second direction, across the first mask patterns. Then, the material layer is patterned by using rest portions of the first mask patterns as a mask to form plural patterns arranged in an array.
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公开(公告)号：US20180233451A1
公开(公告)日：2018-08-16
申请号：US15466881
申请日：2017-03-23
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: H01L23/535 , H01L21/768 , H01L21/3213
CPC classification number: H01L27/10894 , H01L21/76885 , H01L21/76895 , H01L27/10814 , H01L27/10855
Abstract: A method for fabricating a pad structure includes the steps of: providing a material layer; forming an opening in the material layer; forming a conductive layer on the material layer and into the opening; forming a patterned mask on the conductive layer; performing a first etching process to remove part of the conductive layer for forming a conductive plug; and performing a shaping process to alter the shape of a top surface of the conductive plug.
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公开(公告)号：US10049929B2
公开(公告)日：2018-08-14
申请号：US15008453
申请日：2016-01-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Chih-Sen Huang , Po-Chao Tsao , Chieh-Te Chen
IPC: H01L21/4763 , H01L21/768 , H01L29/78 , H01L23/485 , H01L29/66 , H01L21/283 , H01L21/321 , H01L23/528 , H01L29/45 , H01L29/417 , H01L23/532 , H01L29/165
Abstract: The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate.
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