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    SOI DRAM without floating body effect
    51.
    发明授权
    SOI DRAM without floating body effect 有权
    SOI DRAM无浮体效应

    公开(公告)号：US06599797B1

    公开(公告)日：2003-07-29

    申请号：US09980811

    申请日：2002-03-11

    申请人： Franz Hofmann ,  Josef Willer

    发明人： Franz Hofmann ,  Josef Willer

    IPC分类号： H01L218242

    CPC分类号： H01L27/10873 ,  H01L27/10888 ,  H01L27/1203

    摘要： The invention relates to an SOI substrate which is provided with a recess that cuts through the silicon layer and the SiO2 layer (O). An upper part of said recess (V) which is located in the range of the silicon layer (S) has cylindrical shape with a horizontal first cross-section. A lower part of the recess (V) which is located in the range of the SiO2 layer (O), compared with the upper part of the recess (V), is bulged to such an extent that it has a cylindrical shape with a horizontal second cross-section that is larger than the first cross-section. A cylinder (Z) of an insulating material is provided in the recess (V). The horizontal cross-section of said cylinder corresponds to the first cross-section and the lower part thereof is located in the lower part of the recess (V). The dent laterally surrounds the lower part of the cylinder (Z). A conducting structure (L) is located in the dent and adjoins the silicon layer (S) and the silicon substrate (1) so that the channel zone of the MOS transistors is electrically connected to the silicon substrate.

    摘要翻译： 本发明涉及一种SOI衬底，其具有穿过硅层和SiO 2层（O）的凹部。 位于硅层（S）的范围内的所述凹部（V）的上部具有水平的第一横截面的圆筒形状。 与凹部（V）的上部相比，位于SiO 2层（O）的范围内的凹部（V）的下部被凸出到具有水平的圆筒形状的程度 第二横截面大于第一横截面。 在凹部（V）中设置绝缘材料的圆筒（Z）。 所述气缸的水平截面对应于第一横截面，其下部位于凹部（V）的下部。 凹陷横向围绕气缸（Z）的下部。 导电结构（L）位于凹陷中并与硅层（S）和硅衬底（1）相邻，使得MOS晶体管的沟道区电连接到硅衬底。

    DRAM cell arrangement
    54.
    发明授权
    DRAM cell arrangement 有权
    DRAM单元布置

    公开(公告)号：US06492221B1

    公开(公告)日：2002-12-10

    申请号：US09806427

    申请日：2001-07-03

    申请人： Franz Hofmann ,  Josef Willer ,  Till Schloesser

    发明人： Franz Hofmann ,  Josef Willer ,  Till Schloesser

    IPC分类号： H01L218244

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10876

    摘要： A dynamic random access memory includes memory cells arranged in rows and columns on the substrate and a plurality of connecting pillars, each associated with a memory cell. A bit line extends above the main area of the substrate and connects to each memory cell of a column. A first word line connects a first set of alternate memory cells of a row by a first subset of the plurality of connecting pillars. The first word line includes first parts arranged offset relative to the first subset of connecting pillars. A strip-shaped second part extends above the main area and adjoins the first parts of the first word line. A second word line connects to a second set of alternate memory cells of the row by a second subset of the connecting pillars. The second word line includes first parts arranged between mutually adjacent first word lines and offset from the second subset of the connecting pillars. Both the first and second word lines thus overlap but do not cover the connecting pillars. A strip-shaped second part extends above the main area in the first direction and adjoins the first parts of the second word line. The second part is above the first word line and the bit line.

    摘要翻译： 动态随机存取存储器包括以衬底上的行和列布置的存储器单元和多个连接柱，每个连接柱与存储单元相关联。 位线延伸到基板的主区域上方，并连接到列的每个存储单元。 第一字线将一行的第一组备用存储单元与多个连接柱的第一子集连接。 第一字线包括相对于连接柱的第一子集排列的第一部分。 带状第二部分在主区域的上方延伸并与第一字线的第一部分邻接。 第二字线通过连接柱的第二子集连接到该行的第二组替代存储器单元。 第二字线包括布置在彼此相邻的第一字线之间的第一部分和与连接柱的第二子集的偏移。 因此，第一和第二字线都重叠，但不覆盖连接柱。 带状第二部分沿着第一方向延伸到主区域上方并与第二字线的第一部分相邻。 第二部分在第一个字线和位线之上。

    DRAM cell configuration and fabrication method
    55.
    发明授权
    DRAM cell configuration and fabrication method 失效
    DRAM单元配置和制造方法

    公开(公告)号：US06448600B1

    公开(公告)日：2002-09-10

    申请号：US09713484

    申请日：2000-11-15

    申请人： Till Schlösser ,  Franz Hofmann ,  Josef Willer

    发明人： Till Schlösser ,  Franz Hofmann ,  Josef Willer

    IPC分类号： H01L218242

    CPC分类号： H01L27/10867 ,  H01L27/10876 ,  H01L27/10888

    摘要： The memory cells each have a capacitor and a transistor. A storage node of the capacitor is arranged in a first depression formed in a substrate. A gate electrode of the transistor is arranged in a second depression at a first lateral surface of the second depression. The second depression is spaced apart from the first depression. An upper source/drain region of the transistor adjoins the storage node and the second depression. A lower source/drain region of the transistor is formed deeper in the substrate than the upper source/drain region and it adjoins the second depression.

    摘要翻译： 存储单元各自具有电容器和晶体管。 电容器的存储节点布置在形成在基板中的第一凹部中。 晶体管的栅极布置在第二凹陷处的第二凹陷处的第二凹陷处的第一侧表面处。 第二凹陷与第一凹陷间隔开。 晶体管的上源极/漏极区域与存储节点和第二凹陷相邻。 晶体管的下源极/漏极区域在衬底中比上部源极/漏极区域形成得更深，并且与第二凹陷相邻。

    Method for fabricating a memory cell having a MOS transistor
    56.
    发明授权
    Method for fabricating a memory cell having a MOS transistor 有权
    一种具有MOS晶体管的存储单元的制造方法

    公开(公告)号：US06316315B1

    公开(公告)日：2001-11-13

    申请号：US09642328

    申请日：2000-08-21

    申请人： Franz Hofmann ,  Josef Willer

    发明人： Franz Hofmann ,  Josef Willer

    IPC分类号： H01L29788

    CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/7885

    摘要： A memory cell has a vertical MOS transistor which contains a first electrically insulated gate electrode and a second gate electrode. The second gate electrode is partially disposed in a trench whose sidewall is adjoined by the MOS transistor. The first gate electrode is disposed outside the trench and has a tip at an edge of the trench. The tip enables programming with a reduced current flow. The memory cell can be fabricated by self-aligning fabrication with an area requirement of six F2.

    摘要翻译： 存储单元具有垂直MOS晶体管，其包含第一电绝缘栅电极和第二栅电极。 第二栅电极部分地设置在其侧壁与MOS晶体管相邻的沟槽中。 第一栅电极设置在沟槽的外部，并且在沟槽的边缘处具有尖端。 该提示可以减少电流流动进行编程。 存储单元可以通过六对F2的面积要求的自对准制造来制造。

    Integrated circuit with conductive structures
    57.
    发明授权
    Integrated circuit with conductive structures 有权
    具有导电结构的集成电路

    公开(公告)号：US07893519B2

    公开(公告)日：2011-02-22

    申请号：US12128336

    申请日：2008-05-28

    申请人： Franz Hofmann

    发明人： Franz Hofmann

    IPC分类号： H01L29/00

    CPC分类号： H01L27/11521 ,  H01L27/11524

    摘要： An integrated circuit includes an array of transistors and a number of wordlines, where individual ones of the wordlines are coupled to a number of the transistors in the array. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.

    摘要翻译： 集成电路包括晶体管阵列和多个字线，其中字线中的单个字线与阵列中的多个晶体管耦合。 与字线绝缘的导电结构被布置在字线下方的层中，并且布置在晶体管之间。

    Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same
    58.
    发明申请
    Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same 有权
    具有接触区域的集成电路及其制造方法

    公开(公告)号：US20090309152A1

    公开(公告)日：2009-12-17

    申请号：US12137388

    申请日：2008-06-11

    申请人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    发明人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

    摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

    摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。