公开(公告)号：US08008692B2

公开(公告)日：2011-08-30

申请号：US12233486

申请日：2008-09-18

Applicant: Hung-Wei Chen ,  Yider Wu

Inventor： Hung-Wei Chen ,  Yider Wu

IPC: H01L29/04

CPC classification number: H01L29/7881 ,  H01L29/42324 ,  H01L29/7843

Abstract: A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.

Abstract translation: 具有应力区域的半导体存储器结构包括限定第一和第二器件区的衬底; 形成在第一和第二装置区域中的每一个中的第一和第二应力区域以产生不同水平的应力; 将两个装置区彼此分开的阻挡塞; 并且多个氧化物间隔物位于第一应力区域和阻挡塞之间，同时与第一应力区域直接接触。 由于在应力区产生的应力，载流子迁移率增加，因此可以获得增加的读取电流，并且仅需要相对较低的读取电压以获得最初需要的读取电流。 结果，减小了应力诱发漏电流的概率，提高了数据保留能力。

公开(公告)号：US20100065893A1

公开(公告)日：2010-03-18

申请号：US12233486

申请日：2008-09-18

Applicant: Hung-Wei Chen ,  Yider Wu

Inventor： Hung-Wei Chen ,  Yider Wu

IPC: H01L29/04

CPC classification number: H01L29/7881 ,  H01L29/42324 ,  H01L29/7843

Abstract: A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.

Abstract translation: 具有应力区域的半导体存储器结构包括限定第一和第二器件区的衬底; 形成在第一和第二装置区域中的每一个中的第一和第二应力区域以产生不同水平的应力; 将两个装置区彼此分开的阻挡塞; 并且多个氧化物间隔物位于第一应力区域和阻挡塞之间，同时与第一应力区域直接接触。 由于在应力区产生的应力，载流子迁移率增加，因此可以获得增加的读取电流，并且仅需要相对较低的读取电压以获得最初需要的读取电流。 结果，减小了应力诱发漏电流的概率，提高了数据保留能力。

公开(公告)号：US07265014B1

公开(公告)日：2007-09-04

申请号：US10799413

申请日：2004-03-12

Applicant: Angela T. Hui ,  Jusuke Ogura ,  Yider Wu

Inventor： Angela T. Hui ,  Jusuke Ogura ,  Yider Wu

IPC: H01L21/764 ,  H01L29/00

CPC classification number: H01L21/76224

Abstract: A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.

Abstract translation: 一种用于避免半导体器件的浅沟槽隔离（STI）区域中的氧化物气刨的方法和装置。 可以在STI区域中蚀刻沟槽并填充绝缘材料。 抗反射涂层（ARC）层可以沉积在STI区域上并延伸超出STI区域的边界。 可以蚀刻ARC层的一部分，留下ARC层的剩余部分超过STI区域并延伸超出STI区域的边界。 可以沉积保护盖以覆盖ARC层的剩余部分以及绝缘材料。 可以将保护盖回蚀以暴露ARC层。 然而，保护盖仍然覆盖并保护绝缘材料。 通过提供覆盖绝缘材料的保护帽，可以避免STI区域中的绝缘材料的气刨。

公开(公告)号：US20070010055A1

公开(公告)日：2007-01-11

申请号：US11180117

申请日：2005-07-11

Applicant: Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

Inventor： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  H01L27/115 ,  H01L27/11568

Abstract: A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive: layers are formed between two neighboring first dielectric layers in the same row.

Abstract translation: 提供了一种制造非易失性存储器的方法。 在衬底上形成多个隔离结构的列。 在衬底上形成多个跨越隔离结构的层叠栅极结构的行。 在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。 在堆叠栅极结构的侧壁上形成多个隔离条。 多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。 此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。 在同一行中的两个相邻的第一介电层之间形成多个第一导电层。

公开(公告)号：US07151027B1

公开(公告)日：2006-12-19

申请号：US10859369

申请日：2004-06-01

Applicant: Hiroyuki Ogawa ,  Yider Wu ,  Kuo-Tung Chang ,  Yu Sun

Inventor： Hiroyuki Ogawa ,  Yider Wu ,  Kuo-Tung Chang ,  Yu Sun

IPC: H01L21/336

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11548

Abstract: A method and device for reducing interface area of a memory device. A poly-2 layer is formed above a substrate at an interface between a memory array and a periphery of the memory device. The poly-2 layer is etched proximate to the memory array. The poly-2 layer is etched proximate to the periphery such that a portion of the poly-2 layer remains at the interface.

Abstract translation: 一种用于减少存储器件的接口面积的方法和装置。 在存储器阵列和存储器件的外围之间的界面处，在衬底上形成多晶硅层2。 聚二层蚀刻到存储器阵列附近。 聚二层被蚀刻到外围附近，使得多2层的一部分保留在界面处。

公开(公告)号：US20060270142A1

公开(公告)日：2006-11-30

申请号：US11138612

申请日：2005-05-25

Applicant: Kent Chang ,  Jongoh Kim ,  Yider Wu

Inventor： Kent Chang ,  Jongoh Kim ,  Yider Wu

IPC: H01L21/8244

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.

Abstract translation: 描述了一种制造存储器件的方法。 在形成存储单元区域和半导体器件的外围区域的过程中，在形成在栅极的侧壁上的间隔物之前，在存储单元区域上形成光致抗蚀剂层。 因此，在外围电路区域中形成间隔物的过程中，防止存储单元区域被损坏以减轻漏电流问题。

公开(公告)号：US06919247B1

公开(公告)日：2005-07-19

申请号：US10655936

申请日：2003-09-04

Applicant: Yider Wu ,  Kuo-Tung Chang

Inventor： Yider Wu ,  Kuo-Tung Chang

IPC: H01L21/28 ,  H01L21/8247

CPC classification number: H01L21/28273

Abstract: A method of fabricating a floating gate for a semiconductor device is disclosed and provided. According to this method, an undoped polycrystalline silicon layer is deposited on a tunnel oxide layer. The undoped polycrystalline silicon layer has a first thickness. Moreover, a doped polycrystalline silicon layer is deposited on the undoped polycrystalline silicon layer. The doped polycrystalline silicon layer has a second thickness. The undoped polycrystalline silicon layer and the doped polycrystalline silicon layer form the floating gate having a third thickness. In an embodiment, the semiconductor device is a flash memory device.

Abstract translation: 公开并提供了制造用于半导体器件的浮栅的方法。 根据该方法，在隧道氧化物层上沉积未掺杂的多晶硅层。 未掺杂的多晶硅层具有第一厚度。 此外，掺杂的多晶硅层沉积在未掺杂的多晶硅层上。 掺杂多晶硅层具有第二厚度。 未掺杂多晶硅层和掺杂多晶硅层形成具有第三厚度的浮动栅极。 在一个实施例中，半导体器件是闪存器件。

公开(公告)号：US20050151265A1

公开(公告)日：2005-07-14

申请号：US10758148

申请日：2004-01-14

Applicant: Nian Yang ,  Hiroyuki Ogawa ,  Yider Wu ,  Kuo-Tung Chang ,  Yu Sun ,  Darlene Hamilton

Inventor： Nian Yang ,  Hiroyuki Ogawa ,  Yider Wu ,  Kuo-Tung Chang ,  Yu Sun ,  Darlene Hamilton

IPC: G06F17/50 ,  H01L23/485 ,  H01L27/02 ,  H01L23/48 ,  H01L21/44

CPC classification number: H01L27/0203 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014

Abstract: More efficient use of silicon area is achieved by incorporating an active device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is below the first metal layer. The active device resides in the substrate below the second metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the active component. Subsequent metal layers can be arranged between the first and second metal layers.

Abstract translation: 通过在半导体结构的焊盘区域的下方并入有源器件来实现硅面积的更有效的使用。 焊盘区域包括在其上方具有第一金属层的基板。 第二金属层位于第一金属层的下方。 有源器件位于第二金属层下方的衬底中。 电介质层分离第一和第二金属层。 电介质层内的通孔电耦合第一和第二金属层。 A通道连接到活动组件。 随后的金属层可以布置在第一和第二金属层之间。

公开(公告)号：US06869844B1

公开(公告)日：2005-03-22

申请号：US10701780

申请日：2003-11-05

Applicant: Zhizheng Liu ,  Yider Wu ,  Jean Yee-Mei Yang

Inventor： Zhizheng Liu ,  Yider Wu ,  Jean Yee-Mei Yang

IPC: H01L21/336 ,  H01L21/8246 ,  H01L27/02 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/105 ,  H01L27/0248 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

Abstract: A structure for protecting an NROM from induced charge damage during device fabrication is described. The structure provides a discharge path for charge accumulated on the polygate layer during fabrication while providing sufficient isolation to ensure normal circuit operation.

Abstract translation: 描述了在器件制造期间保护NROM免受感应电荷损伤的结构。 该结构提供了在制造期间积聚在多晶硅层上的电荷的放电路径，同时提供足够的隔离以确保正常的电路操作。

公开(公告)号：US06754106B1

公开(公告)日：2004-06-22

申请号：US10245146

申请日：2002-09-16

Applicant: Yider Wu ,  Jean Yang ,  Jiang Li

Inventor： Yider Wu ,  Jean Yang ,  Jiang Li

IPC: G11C1606

CPC classification number: G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

Abstract: A load circuit for compensating for source side loading effects in a non-volatile memory. Specifically, embodiments of the present invention describe a reference cell that is coupled to a plurality of load circuits. At least one of the plurality of load circuits, an mth load circuit, comprises a select transistor coupled to m resistors that are coupled in series. The mth load circuit matches a source side loading effect of a corresponding mth memory cell located m memory cells away from a source line node on a source line coupling source regions in memory cells of a row of memory cells.

Abstract translation: 用于补偿非易失性存储器中源侧负载效应的负载电路。 具体地，本发明的实施例描述了耦合到多个负载电路的参考单元。 多个负载电路中的至少一个负载电路包括耦合到串联耦合的m个电阻器的选择晶体管。 第m个负载电路将位于m个存储单元的相应的第m个存储器单元的源极负载效应与源极线上的源极线节点耦合，该源极线耦合存储器单元的行的存储器单元中的源极区域。