公开(公告)号：US08859348B2

公开(公告)日：2014-10-14

申请号：US13544093

申请日：2012-07-09

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Devendra K. Sadana

IPC分类号： H01L21/84

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： A method for fabricating field effect transistors patterns a strained silicon layer formed on a dielectric layer of a substrate into at least one NFET region including at least a first portion of the strained silicon layer. The strained silicon layer is further patterned into at least one PFET region including at least a second portion of the strained silicon layer. A masking layer is formed over the first portion of the strained silicon layer. After the masking layer has been formed, the second strained silicon layer is transformed into a relaxed silicon layer. The relaxed silicon layer is transformed into a strained silicon germanium layer.

摘要翻译： 用于制造场效应晶体管的方法将形成在衬底的电介质层上的应变硅层图案化成至少一个包括应变硅层的第一部分的NFET区域。 将应变硅层进一步图案化成至少一个包括应变硅层的至少第二部分的PFET区域。 在应变硅层的第一部分上形成掩模层。 在形成掩模层之后，将第二应变硅层转变成松弛的硅层。 松弛的硅层被转变成应变硅锗层。

公开(公告)号：US08659066B2

公开(公告)日：2014-02-25

申请号：US13345266

申请日：2012-01-06

申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC分类号： H01L27/06

CPC分类号： H01L21/84 ,  H01L21/32053 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/41783

摘要： An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.

摘要翻译： 集成电路包括晶体管和电容器。 晶体管包括位于第一半导体层上的第一半导体层和栅极堆叠。 栅堆叠包括金属层和第一高k电介质层。 栅极间隔物位于栅极叠层的侧壁上。 第一高k电介质层位于第一半导体层和金属层之间以及栅间隔物和金属层的侧壁之间。 第一硅化物区域位于第一源极/漏极区域上。 第二硅化物区域位于第二源极/漏极区域上。 电容器包括第一端子，其包括位于第二半导体的一部分上的第三硅化物区域。 第二高k电介质层位于硅化物区域上。 第二端子包括位于第二高k电介质层上的金属层。

公开(公告)号：US20110254090A1

公开(公告)日：2011-10-20

申请号：US12760250

申请日：2010-04-14

申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L29/78654 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78618

摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.

摘要翻译： 提供一种晶体管，其包括衬底上方的掩埋氧化物层。 硅层在掩埋氧化物层之上。 栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。 氮化物衬垫与栅堆叠相邻。 氧化物衬垫与氮化物衬垫相邻。 一组具有包括硅层的一部分的部分的凸起的源/漏区。 所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

公开(公告)号：US20070152276A1

公开(公告)日：2007-07-05

申请号：US11323578

申请日：2005-12-30

申请人： John Arnold ,  Glenn Biery ,  Alessandro Callegari ,  Tze-Chiang Chen ,  Michael Chudzik ,  Bruce Doris ,  Michael Gribelyuk ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Joseph Newbury ,  Vamsi Paruchuri ,  Michelle Steen

发明人： John Arnold ,  Glenn Biery ,  Alessandro Callegari ,  Tze-Chiang Chen ,  Michael Chudzik ,  Bruce Doris ,  Michael Gribelyuk ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Joseph Newbury ,  Vamsi Paruchuri ,  Michelle Steen

IPC分类号： H01L29/94

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.

摘要翻译： 本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。 第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的 门导体。 第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。 可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

公开(公告)号：US20060237796A1

公开(公告)日：2006-10-26

申请号：US11111592

申请日：2005-04-21

申请人： Eduard Cartier ,  Matthew Copel ,  Bruce Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Keith Wong

发明人： Eduard Cartier ,  Matthew Copel ,  Bruce Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry Linder ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Keith Wong

IPC分类号： H01L29/76

CPC分类号： H01L21/823842

摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a worfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

摘要翻译： 本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。 根据本发明，至少一个nMOS器件包括栅堆叠，其包括栅极电介质，功能小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及 所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。 本发明还提供了制造这种CMOS结构的方法。

公开(公告)号：US20060172495A1

公开(公告)日：2006-08-03

申请号：US10905978

申请日：2005-01-28

申请人： Huilong Zhu ,  Bruce Doris ,  Philip Oldiges ,  Meikel Ioeng ,  Min Yang ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce Doris ,  Philip Oldiges ,  Meikel Ioeng ,  Min Yang ,  Huajie Chen

IPC分类号： H01L21/8234

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1207 ,  Y10S438/938

摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.

摘要翻译： 本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

公开(公告)号：US20060157706A1

公开(公告)日：2006-07-20

申请号：US11037622

申请日：2005-01-18

申请人： Huilong Zhu ,  Bruce Doris ,  Huajie Chen ,  Patricia Mooney ,  Stephen Bedell

发明人： Huilong Zhu ,  Bruce Doris ,  Huajie Chen ,  Patricia Mooney ,  Stephen Bedell

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

摘要： The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

摘要翻译： 本发明提供了具有多个结晶取向的应变Si直接绝缘体（SSDOI）基板及其形成方法。 广义上，但是具体来说，本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层，所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向，并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。 第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

公开(公告)号：US07041600B2

公开(公告)日：2006-05-09

申请号：US10604196

申请日：2003-06-30

申请人： Omer Dokumaci ,  Bruce Doris ,  David Horak ,  Fen F. Jamin

发明人： Omer Dokumaci ,  Bruce Doris ,  David Horak ,  Fen F. Jamin

IPC分类号： H10L21/302

CPC分类号： H01L21/31053

摘要： A method of planarization allows for the use of chemical mechanical polishing (CMP) in starting structures having films not generally suitable for CMP processes. Two material layers are formed over a starting structure, and the upper layer is planarized in a CMP process. A nonselective etch is then used to transfer the planar topography to the lower level.

摘要翻译： 平面化方法允许在起始结构中使用化学机械抛光（CMP），其具有通常不适用于CMP工艺的膜。 在起始结构上形成两个材料层，并且在CMP工艺中将上层平坦化。 然后使用非选择性蚀刻将平面形貌转移到较低水平。

公开(公告)号：US20050275060A1

公开(公告)日：2005-12-15

申请号：US11151506

申请日：2005-06-13

申请人： Omer Dokumaci ,  Bruce Doris

发明人： Omer Dokumaci ,  Bruce Doris

IPC分类号： H01L21/76 ,  H01L21/301 ,  H01L21/311 ,  H01L21/318 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/02271 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/31144 ,  H01L21/3185 ,  H01L21/76224 ,  H01L21/76283

摘要： Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.

摘要翻译： 公开了一种保护半导体浅沟槽隔离（STI）氧化物免受蚀刻的方法，所述方法包括如果需要，将所述STI氧化物的上表面降低至低于相邻硅有源区的上表面，将氮化物衬垫沉积在所述 STI氧化物和相邻的硅有源区，以有效地限定所述STI氧化物上方的凹陷的方式，用保护膜填充所述凹陷，以及从所述相邻的活性区域移除所述氮化物层。

公开(公告)号：US20050245017A1

公开(公告)日：2005-11-03

申请号：US11175223

申请日：2005-07-07

申请人： Michael Belyansky ,  Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Oleg Glusehenkov

发明人： Michael Belyansky ,  Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Oleg Glusehenkov

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/302 ,  H01L21/336 ,  H01L21/44 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/72 ,  H01L29/78 ,  H01L29/786 ,  H01L31/062

CPC分类号： H01L29/7845 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785

摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.