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    DATA DEVICES INCLUDING MULTIPLE ERROR CORRECTION CODES AND METHODS OF UTILIZING
    51.
    发明申请
    DATA DEVICES INCLUDING MULTIPLE ERROR CORRECTION CODES AND METHODS OF UTILIZING 有权
    包含多个错误修正码的数据设备和使用方法

    公开(公告)号：US20100058125A1

    公开(公告)日：2010-03-04

    申请号：US12198516

    申请日：2008-08-26

    申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1048 ,  G11C2029/0411

    摘要： A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.

    摘要翻译： 一种使用至少一个数据块的方法，其中所述至少一个数据块包括用于存储数据的多个单元和至少一个误差标志位，所述方法包括：扫描所述数据块的错误; 确定数据块的错误率; 以及对所述至少一个数据块中的单元读取或写入的数据应用纠错码，其中，基于所述错误率应用所述纠错码，其中当所述错误率 低于错误阈值，并且当错误率处于或高于错误阈值时应用强纠错码。

    TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT
    52.
    发明申请
    TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT 有权
    基于传输门控的转子转矩记忆单元

    公开(公告)号：US20100008134A1

    公开(公告)日：2010-01-14

    申请号：US12170549

    申请日：2008-07-10

    申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

    发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  Y10S977/935

    摘要： A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

    摘要翻译： 描述基于传输门的自旋转移转矩存储单元。 存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 NMOS晶体管与PMOS晶体管并联电连接，并且它们与源极线和磁性隧道结数据单元电连接。 磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 PMOS晶体管和NMOS晶体管可单独寻址，使得第一方向上的第一写入电流流过PMOS晶体管，并且第二方向的第二写入电流流过NMOS晶体管。

    Bipolar CMOS select device for resistive sense memory
    53.
    发明授权
    Bipolar CMOS select device for resistive sense memory 有权
    用于电阻读出存储器的双极CMOS选择器件

    公开(公告)号：US09030867B2

    公开(公告)日：2015-05-12

    申请号：US12502211

    申请日：2009-07-13

    申请人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

    发明人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

    IPC分类号： G11C11/00 ,  G11C11/34 ,  G11C13/00 ,  G11C11/16

    CPC分类号： G11C13/0004 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/76

    摘要： A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.

    摘要翻译： 电阻式感测存储装置包括具有半导体衬底和设置在半导体衬底中并形成行或晶体管的多个晶体管的双极选择器件。 每个晶体管包括发射极触点和集电极触点。 每个集电极触点彼此电隔离，并且每个发射极触点彼此电隔离。 栅极触点沿发射极触点和集电极触点之间的沟道区域延伸。 基极触点设置在半导体衬底内，使得发射极触点和集电极触点位于栅极触点和基极触点之间。 电阻读出存储单元电耦合到每个集电极触点或发射极触点和位线。

    BIPOLAR CMOS SELECT DEVICE FOR RESISTIVE SENSE MEMORY
    54.
    发明申请
    BIPOLAR CMOS SELECT DEVICE FOR RESISTIVE SENSE MEMORY 有权
    BIPOLAR CMOS选择器件，用于电阻式感应存储器

    公开(公告)号：US20100177554A1

    公开(公告)日：2010-07-15

    申请号：US12502211

    申请日：2009-07-13

    申请人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

    发明人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

    IPC分类号： G11C11/00 ,  G11C11/14

    CPC分类号： G11C13/0004 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/76

    摘要： A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.

    摘要翻译： 电阻式感测存储装置包括具有半导体衬底和设置在半导体衬底中并形成行或晶体管的多个晶体管的双极选择器件。 每个晶体管包括发射极触点和集电极触点。 每个集电极触点彼此电隔离，并且每个发射极触点彼此电隔离。 栅极触点沿发射极触点和集电极触点之间的沟道区域延伸。 基极触点设置在半导体衬底内，使得发射极触点和集电极触点位于栅极触点和基极触点之间。 电阻读出存储单元电耦合到每个集电极触点或发射极触点和位线。

    DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF
    57.
    发明申请
    DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF 审中-公开
    基于线路的双重存储器阵列和存储器单元

    公开(公告)号：US20100118602A1

    公开(公告)日：2010-05-13

    申请号：US12270056

    申请日：2008-11-13

    申请人： Andrew John Carter ,  Yiran Chen ,  Yong Lu ,  Harry Hongyue Liu

    发明人： Andrew John Carter ,  Yiran Chen ,  Yong Lu ,  Harry Hongyue Liu

    IPC分类号： G11C11/14

    CPC分类号： G11C5/063 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2213/72 ,  G11C2213/74

    摘要： A memory array includes a plurality of first and second source, lines overlapping a plurality of bit lines, and a plurality of magnetic storage elements, each coupled to a corresponding first and second source line and to a corresponding bit line. Current may be driven, in first and second directions, through each magnetic element, for example, to program the elements. Diodes may be incorporated to avert sneak paths in the memory array. A first diode may be coupled between each magnetic element and the corresponding first source line, the first diode being biased to allow read and write current flow through the magnetic element, from the corresponding first source line; and a second diode may be coupled between each magnetic element and the corresponding second source line, the second diode being reverse-biased to block read and write current flow through the magnetic element, from the corresponding second source line.

    摘要翻译： 存储器阵列包括多个第一和第二源，与多个位线重叠的线，以及多个磁存储元件，每个磁存储元件分别耦合到对应的第一和第二源极线以及相应的位线。 电流可以在第一和第二方向上通过每个磁性元件被驱动，例如编程元件。 可以并入二极管以避免存储器阵列中的潜行路径。 第一二极管可以耦合在每个磁性元件和对应的第一源极线之间，第一二极管被偏置以允许读取和写入电流从相应的第一源极线流过磁性元件; 并且第二二极管可以耦合在每个磁性元件和对应的第二源极线之间，所述第二二极管被反向偏置以阻挡从对应的第二源极线读取和写入通过磁性元件的电流。

    Spin-transfer torque memory non-destructive self-reference read method
    58.
    发明授权
    Spin-transfer torque memory non-destructive self-reference read method 有权
    旋转转矩记忆无损自参考读取方法

    公开(公告)号：US08416614B2

    公开(公告)日：2013-04-09

    申请号：US13349044

    申请日：2012-01-12

    申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Ran Wang ,  Dimitar V. Dimitrov

    发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Ran Wang ,  Dimitar V. Dimitrov

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1673 ,  G11C11/1693

    摘要： A method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state. The first read current is less than the second read current. Then the first bit line read voltage is compared with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

    摘要翻译： 自参考读取自旋传递扭矩存储单元的方法包括：通过磁性隧道结数据单元施加第一读取电流并形成第一位线读取电压。 磁性隧道结数据单元具有第一电阻状态。 然后，该方法包括通过具有第一电阻状态的磁性隧道结数据单元施加第二读取电流。 第一个读取电流小于第二个读取电流。 然后将第一位线读取电压与第二位线读取电压进行比较，以确定磁性隧道结数据单元的第一电阻状态是高电阻状态还是低电阻状态。

    Spatial correlation of reference cells in resistive memory array
    59.
    发明授权
    Spatial correlation of reference cells in resistive memory array 有权
    参考电池在电阻式存储器阵列中的空间相关性

    公开(公告)号：US08139397B2

    公开(公告)日：2012-03-20

    申请号：US12968438

    申请日：2010-12-15

    申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

    发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

    IPC分类号： G11C11/00

    CPC分类号： G11C5/025 ,  G11C11/1653 ,  G11C11/1673

    摘要： The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory cell to form a map of the resistance state resistance values for a plurality of variable resistive memory cells within a memory array. Then a column or row is selected to be a reference column or reference row based on the map of the resistance state resistance value for a plurality of variable resistive memory cells within a memory array, to minimize read operation errors, and forming a variable resistive memory cell memory array.

    摘要翻译： 本公开涉及将参考列或参考行选择性地放置在存储器阵列中的方法。 该方法包括测量存储器阵列内的多个可变电阻存储器单元的电阻状态电阻值，并映射每个测量的可变电阻存储单元的位置，以形成多个可变电阻存储单元的电阻状态电阻值的映射 在内存阵列内。 然后，基于存储器阵列内的多个可变电阻存储器单元的电阻状态电阻值的映射来选择列或行作为参考列或参考行，以最小化读取操作错误，以及形成可变电阻存储器 单元存储器阵列。