公开(公告)号：US6023757A

公开(公告)日：2000-02-08

申请号：US791811

申请日：1997-01-30

申请人： Junichi Nishimoto ,  Hideo Maejima

发明人： Junichi Nishimoto ,  Hideo Maejima

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/16

CPC分类号： G06F9/3822 ,  G06F9/30149 ,  G06F9/30196 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3885

摘要： A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

公开(公告)号：US5696540A

公开(公告)日：1997-12-09

申请号：US799889

申请日：1991-12-02

申请人： Koyo Katsura ,  Hideo Maejima ,  Hiroshi Takeda

发明人： Koyo Katsura ,  Hideo Maejima ,  Hiroshi Takeda

IPC分类号： G06F3/153 ,  G06F3/14 ,  G09G1/02 ,  G09G5/14 ,  G09G5/32 ,  G09G5/36 ,  G09G5/377 ,  G09G5/39 ,  G09G5/395 ,  G09G5/397 ,  G09G1/00

CPC分类号： G09G5/36 ,  G09G5/363 ,  G09G5/39 ,  G09G5/397

摘要： In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted to or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.

摘要翻译： 在根据显示装置的高集成度存在将增加要处理的数据的趋势的图像显示领域中，根据本发明的CRT控制器改进了叠加显示和显示和绘图操作的响应性 通过将单位时钟分割成预定数量以高速功能和多功能显示。 当图像数据要被输入到与显示帧相对应的刷新存储器中时，以1：n的比例分配存储器内容和显示地址以并行地进行处理。 结果，可以将现有技术的显示循环所使用的时间段分配给绘制操作，使得可以加速处理，同时使现有技术更容易实现字母，符号和图纸的叠加显示 。 所产生的效果是不需要增加对应于所显示的帧的刷新存储器的数量，并且可以简化外部部件以有助于提高可靠性。

公开(公告)号：US5657045A

公开(公告)日：1997-08-12

申请号：US430851

申请日：1995-04-28

申请人： Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

发明人： Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

IPC分类号： G06T1/20 ,  G06T1/60 ,  G06T11/20 ,  G06T17/00 ,  G09G5/02 ,  G09G5/20 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399 ,  G09G5/38

CPC分类号： G09G5/395 ,  G06T1/20 ,  G06T1/60 ,  G06T11/203 ,  G06T17/00 ,  G09G5/024 ,  G09G5/20 ,  G09G5/363 ,  G09G5/39 ,  G09G5/393 ,  G09G5/399 ,  G09G2360/127 ,  G09G5/36

摘要： A graphic data generating apparatus includes a data processor, a graphic memory, and a graphic processor. The data processor outputs instructions to the graphic processor for processing graphic data. The instructions include a drawing instruction for transferring graphic data stored in a predetermined location in the graphic memory to another predetermined location in the graphic memory. The graphic memory stores pixel data defining the graphic data and each of the pixel data having a plurality of bits. The graphic processor performing read out of word data having a plurality of pixel data at a word position of the graphic memory specified by a source memory address, selecting pixel data specified by a source pixel address in the readout word and writing the selected pixel data in the graphic memory at a pixel position specified by a destination pixel address of word data specified by the destination memory address.

摘要翻译： 图形数据生成装置包括数据处理器，图形存储器和图形处理器。 数据处理器向图形处理器输出指令以处理图形数据。 指令包括用于将存储在图形存储器中的预定位置的图形数据传送到图形存储器中的另一预定位置的绘图指令。 图形存储器存储定义图形数据的像素数据，并且每个像素数据具有多个位。 图形处理器执行读出由源存储器地址指定的图形存储器的字位置处的多个像素数据的字数据，选择由读出字中的源像素地址指定的像素数据，并将所选择的像素数据写入 在由目的地存储器地址指定的字数据的目标像素地址指定的像素位置处的图形存储器。

公开(公告)号：US5187782A

公开(公告)日：1993-02-16

申请号：US552117

申请日：1990-07-13

申请人： Ikuya Kawasaki ,  Keiichi Kurakazu ,  Hideo Maejima

发明人： Ikuya Kawasaki ,  Keiichi Kurakazu ,  Hideo Maejima

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3822 ,  G06F9/30149 ,  G06F9/3824

摘要： An instruction is constituted by a plurality of words, minimum necessary information necessary for effective address calculation of an operand is stored in a leading word and a word or words containing an operation specification field (operation words) are arranged to continue the first word. According to this system, the operation word can be decoded concurrently with the address calculation of the operand or the operand fetch operation. Therefore, there is no need to secure a time exclusively for decoding the operation word and the execution speed of the instruction requiring the operand can be improved.

摘要翻译： 指令由多个字构成，操作数的有效地址计算所需的最小必要信息被存储在前导字中，并且包括操作指定字段（操作字）的字或字被布置成继续第一个字。 根据该系统，可以与操作数的地址计算或操作数获取操作同时解码操作字。 因此，不需要仅为解码操作字确保时间，并且可以提高需要操作数的指令的执行速度。

公开(公告)号：US5117382A

公开(公告)日：1992-05-26

申请号：US618114

申请日：1990-11-26

申请人： Hideo Maejima ,  Takashi Hotta ,  Ikuro Masuda ,  Masahiro Iwamura ,  Kouzaburou Kurita ,  Masahiro Ueno

发明人： Hideo Maejima ,  Takashi Hotta ,  Ikuro Masuda ,  Masahiro Iwamura ,  Kouzaburou Kurita ,  Masahiro Ueno

IPC分类号： G06F5/01 ,  G06F7/50 ,  G06F7/508 ,  G06F13/40 ,  G06F15/78

CPC分类号： G06F7/508 ,  G06F13/4077 ,  G06F15/7832 ,  G06F5/015 ,  G06F2207/3872 ,  Y02B60/1207 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A semiconductor integrated circuit is provided for performing an arithmetic operation using an arithmetic operation circuit. The integrated circuit includes a read bus for connecting the arithmetic operation circuit with a plurality of registers which store input data and/or output data of said arithmetic operation circuit. A precharge and sense circuit connects said arithmetic operation circuit to said read bus. The precharge and sense circuit includes a precharge circuit to precharge the read bus to a first level before the read operation, and a sense circuit to detect that the level of the read bus has discharged to a second, lower level after the read operation begins. In this way, the integrated circuit can detect very slight potential variations on said read bus.

公开(公告)号：US5047669A

公开(公告)日：1991-09-10

申请号：US318689

申请日：1989-03-03

申请人： Masahiro Iwamura ,  Kozaburo Kurita ,  Hideo Maejima ,  Tetsuo Nakano ,  Atsuo Hotta

发明人： Masahiro Iwamura ,  Kozaburo Kurita ,  Hideo Maejima ,  Tetsuo Nakano ,  Atsuo Hotta

IPC分类号： H03K17/567 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/094 ,  H03K19/0944

CPC分类号： H03K17/567 ,  H03K19/00307 ,  H03K19/09429 ,  H03K19/09448

摘要： In a semiconductor integrated circuit, drain-source paths of an NMOS transistor and a PMOS transistor are connected between the base and emitter of a bipolar transistor, and control signals are applied to gates of the NMOS transistor and the PMOS transistor so as to keep the NMOS transistor and the PMOS transistor at OFF condition when the bipolar transistor is operating and so as to keep the NMOS transistor and the PMOS transistor at ON condition when the bipolar transistor is in the quiescent state.

公开(公告)号：US4849658A

公开(公告)日：1989-07-18

申请号：US81696

申请日：1987-08-04

申请人： Masahiro Iwamura ,  Takashi Hotta ,  Hideo Maejima

发明人： Masahiro Iwamura ,  Takashi Hotta ,  Hideo Maejima

IPC分类号： H03K19/08 ,  G06F7/50 ,  G06F7/501 ,  G11C7/12 ,  H03K19/096 ,  H03K19/177

CPC分类号： G06F7/5016 ,  G11C7/12 ,  H03K19/0963 ,  H03K19/1772 ,  G06F2207/3872

摘要： A dynamic logic circuit is provided which is arranged to realize high speed operation. At least one bipolar transistor is provided having a collector, a base and an emitter, with the collector-emitter current path connected between the output of the dynamic logic circuit and a first potential. A precharging device is coupled between a second potential and the output of the dynamic logic circuit to precharge the output according to at least one clock signal which periodically changes its state. Further, at least two field-effect transistors are provided, wherein one assumes an on or off state opposite to that of the precharging means in response to the clock signal while the other operates in response to at least one input signal. The two field-effect transistors have their source-drain current paths connected between the output of the dynamic logic circuit and the base of the bipolar transistor.

摘要翻译： 提供了一种实现高速运行的动态逻辑电路。 提供至少一个具有集电极，基极和发射极的双极晶体管，其中集电极 - 发射极电流路径连接在动态逻辑电路的输出端和第一电位之间。 预充电装置耦合在第二电位和动态逻辑电路的输出端之间，以根据周期性地改变其状态的至少一个时钟信号对输出进行预充电。 此外，提供了至少两个场效应晶体管，其中响应于时钟信号而假定与预充电装置相反的导通或截止状态，而另一个响应于至少一个输入信号而工作。 两个场效应晶体管的源极 - 漏极电流路径连接在动态逻辑电路的输出端和双极晶体管的基极之间。

公开(公告)号：US4727517A

公开(公告)日：1988-02-23

申请号：US785654

申请日：1985-10-09

申请人： Masahiro Ueno ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Ikuro Masuda ,  Tetsuo Nakano

发明人： Masahiro Ueno ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Ikuro Masuda ,  Tetsuo Nakano

IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C7/00

CPC分类号： G11C5/147 ,  G11C7/12

摘要： A semiconductor memory is provided including a plurality of row lines, memory cells driven by selecting a row line, sense amplifiers connected to the memory cells via column lines, and a column line voltage setting circuit for setting a predetermined voltage on the column lines. The predetermined voltage is defined by a voltage necessary to activate semiconductor switch elements constituting the column line voltage setting circuit, and is made nearly equal to the threshold voltage of the sense amplifiers. Thus, a high-speed, low power consumption semiconductor memory can be realized.

摘要翻译： 提供一种半导体存储器，其包括多条行线，通过选择行线驱动的存储单元，经由列线连接到存储单元的读出放大器，以及用于在列线上设置预定电压的列线电压设置电路。 预定电压由激活构成列线电压设定电路的半导体开关元件所需的电压限定，并且使其几乎等于读出放大器的阈值电压。 因此，可以实现高速，低功耗的半导体存储器。

公开(公告)号：US4677549A

公开(公告)日：1987-06-30

申请号：US469047

申请日：1983-02-23

申请人： Koyo Katsura ,  Hideo Maejima

发明人： Koyo Katsura ,  Hideo Maejima

IPC分类号： G06F9/38 ,  G06F9/22 ,  G06F9/28 ,  G06F13/00

CPC分类号： G06F9/3824 ,  G06F9/28

摘要： The invention relates to a digital data processor based upon the pipeline control system, which is particularly effective when the time required for reading a microprogram is relatively short. A microcycle is based upon the time required for reading the microprogram, and the operations on the data is executed in a pipeline system by dividing it up according to the determined microcycle. This is done by providing a destination latch register on the output side of the arithmetic unit. The invention further deals with the processors in which the destination latch register is provided on the input side of the arithmetic unit, or when the destination latch register is incorporated within the arithmetic unit, and a circuit setup for avoiding any contention for a register that may develop when executing a current instruction and the next instruction is provided in accordance with an added microprogram.

摘要翻译： 本发明涉及一种基于流水线控制系统的数字数据处理器，当读取微程序所需的时间相对较短时，该处理器特别有效。 微循环基于读取微程序所需的时间，并且通过根据确定的微循环将其分割在管道系统中来执行对数据的操作。 这通过在算术单元的输出侧提供目的地锁存寄存器来完成。 本发明还涉及其中目的地锁存寄存器被提供在运算单元的输入侧上，或者当目的地锁存寄存器被并入运算单元内的处理器，以及用于避免任何可能对寄存器进行争用的电路设置 在执行当前指令时产生，并且根据添加的微程序提供下一指令。

公开(公告)号：US4523276A

公开(公告)日：1985-06-11

申请号：US533803

申请日：1983-09-19

申请人： Hideo Maejima ,  Ikuro Masuda ,  Hidekazu Matsumoto ,  Shyoichi Miyazawa

发明人： Hideo Maejima ,  Ikuro Masuda ,  Hidekazu Matsumoto ,  Shyoichi Miyazawa

IPC分类号： G06F13/36 ,  G06F12/04 ,  G06F12/06 ,  G06F15/16 ,  G06F15/177 ,  G06F5/00 ,  G06F13/00

CPC分类号： G06F12/04

摘要： An input/output control device stores variable-length data in a memory device at a high storage efficiency and without reducing the speed of data processing. The data stored in a memory are read out in the form of data of a fixed word length and then processed, the data having been processed are stored in another memory in the form of data of the fixed word length. The data stored in another memory are subjected to data organization to be outputted in the form of data of a given word length. Each of the memories is divided into a plurality of regions, and each region stores therein data of the same word length, respectively.

摘要翻译： 输入/输出控制装置以高存储效率将可变长度数据存储在存储装置中，而不降低数据处理的速度。 存储在存储器中的数据以固定字长的数据的形式读出，然后被处理，已经处理的数据以固定字长的数据的形式存储在另一个存储器中。 存储在另一存储器中的数据经受数据组织以以给定字长的数据的形式输出。 每个存储器被分成多个区域，并且每个区域分别存储相同字长的数据。