公开(公告)号：US4523276A

公开(公告)日：1985-06-11

申请号：US533803

申请日：1983-09-19

申请人： Hideo Maejima ,  Ikuro Masuda ,  Hidekazu Matsumoto ,  Shyoichi Miyazawa

发明人： Hideo Maejima ,  Ikuro Masuda ,  Hidekazu Matsumoto ,  Shyoichi Miyazawa

IPC分类号： G06F13/36 ,  G06F12/04 ,  G06F12/06 ,  G06F15/16 ,  G06F15/177 ,  G06F5/00 ,  G06F13/00

CPC分类号： G06F12/04

摘要： An input/output control device stores variable-length data in a memory device at a high storage efficiency and without reducing the speed of data processing. The data stored in a memory are read out in the form of data of a fixed word length and then processed, the data having been processed are stored in another memory in the form of data of the fixed word length. The data stored in another memory are subjected to data organization to be outputted in the form of data of a given word length. Each of the memories is divided into a plurality of regions, and each region stores therein data of the same word length, respectively.

摘要翻译： 输入/输出控制装置以高存储效率将可变长度数据存储在存储装置中，而不降低数据处理的速度。 存储在存储器中的数据以固定字长的数据的形式读出，然后被处理，已经处理的数据以固定字长的数据的形式存储在另一个存储器中。 存储在另一存储器中的数据经受数据组织以以给定字长的数据的形式输出。 每个存储器被分成多个区域，并且每个区域分别存储相同字长的数据。

公开(公告)号：US4454578A

公开(公告)日：1984-06-12

申请号：US265168

申请日：1981-05-19

申请人： Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hideo Maejima

发明人： Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hideo Maejima

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/42 ,  G06F9/36

CPC分类号： G06F9/30192 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3889

摘要： A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retaining instructions from a memory and alignment means for aligning the instructions from the instruction buffer such that the instruction includes at least one operand specifier in one machine cycle, and provides it to a decoding unit. The decoding unit includes an operation code decoder and two operand specifier decoders to decode two operand specifiers simultaneously when the last operand specifier is a register designation mode. Each of the units executes instructions in a pipelined fashion and processes operands in a pipelined fashion.

摘要翻译： 一种用于执行可变长度指令的数据处理单元，其中用于指定操作数的寻址模式的操作数说明符与用于确定操作的操作代码无关。 指令提取单元包括用于从存储器预取和保存指令的指令缓冲器以及用于对准来自指令缓冲器的指令的对准装置，使得指令在一个机器周期中包括至少一个操作数说明符，并将其提供给解码单元。 解码单元包括操作码解码器和两个操作数说明符解码器，以在最后一个操作数说明符是寄存器指定模式时同时解码两个操作数说明符。 每个单元以流水线方式执行指令，并以流水线方式处理操作数。

公开(公告)号：US4896258A

公开(公告)日：1990-01-23

申请号：US881407

申请日：1986-07-02

申请人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hiroaki Nakanishi ,  Kenzi Hirose ,  Takao Kobayashi ,  Yoshihiro Miyazaki

发明人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hiroaki Nakanishi ,  Kenzi Hirose ,  Takao Kobayashi ,  Yoshihiro Miyazaki

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/44

CPC分类号： G06F9/30181 ,  G06F9/30061 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30192 ,  G06F9/3557 ,  G06F9/4438

摘要： A data processor for execution of tagged data and tagless data has a decoder for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part for extracting the tag part from data on a data bus, a plurality of tag part storing registers for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.

公开(公告)号：US5146569A

公开(公告)日：1992-09-08

申请号：US674398

申请日：1991-03-25

申请人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Morioka Takayuki ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

发明人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Morioka Takayuki ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

IPC分类号： G06F11/14

CPC分类号： G06F11/141

摘要： Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

摘要翻译： 微程序控制数据处理装置中的指令重新开始处理的方法和装置，其中，在指令暂停之后重启指令执行时，指令执行暂停时的数据处理装置的内部信息被保存在存储器中，之后 暂停原因清除过程执行保存的内部信息被恢复。 根据微程序的指定，存储与当前执行的微程序地址相关联的检查点地址。 暂停之后，执行删除处理，指令的执行使用检查点地址重新开始。 如果在暂停原因移除处理被执行之后没有存储检查点地址，则从主存储器的暂停指令的读取操作重新开始指令的执行。

公开(公告)号：US4523272A

公开(公告)日：1985-06-11

申请号：US366785

申请日：1982-04-08

申请人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Ryosei Hiraoka ,  Hidekazu Matsumoto ,  Jushi Ide ,  Tetsuya Kawakami

发明人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Ryosei Hiraoka ,  Hidekazu Matsumoto ,  Jushi Ide ,  Tetsuya Kawakami

IPC分类号： G06F13/374 ,  G06F15/16 ,  G06F15/40

CPC分类号： G06F13/374

摘要： In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.

摘要翻译： 在具有主存储器和通过公共地址总线连接的多个处理器，数据总线和用于数据传送的应答总线的多处理器系统中，为每个主存储器和处理器提供数据传输装置，并且包括总线请求控制线， 传送总线请求信号和总线控制信号;以及总线控制器，用于响应于总线请求控制线上的信号和请求信号单独控制地址总线，数据总线和应答总线的选择。 可以在一个周期内重叠处理，如数据写入和数据写入应答或数据读取和数据读取应答。

公开(公告)号：US4481573A

公开(公告)日：1984-11-06

申请号：US320934

申请日：1981-11-13

申请人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Ryosei Hiraoka ,  Jushi Ide ,  Takeshi Kato ,  Tetsuya Kawakami

发明人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Ryosei Hiraoka ,  Jushi Ide ,  Takeshi Kato ,  Tetsuya Kawakami

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/00

CPC分类号： G06F12/1081 ,  G06F12/0833 ,  G06F12/1045

摘要： A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to execute an instruction and includes a cache memory which is accessed with a virtual address. One of the plurality of processors is a file processor which accesses the main memory with a virtual address to transfer data between the main memory and an external memory. The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

摘要翻译： 公开了一种具有地址转换单元的虚拟存储数据处理系统，该地址转换单元由位于连接到主存储器的存储器控​​制单元中的多个处理器共享。 多个处理器之一是作业处理器，其以虚拟地址访问主存储器以执行指令，并且包括用虚拟地址访问的高速缓冲存储器。 多个处理器之一是文件处理器，其以虚拟地址访问主存储器，以在主存储器和外部存储器之间传送数据。 当文件处理器写入主存储器时，缓存存储器接收虚拟地址，并且如果其包含与虚拟地址相对应的数据块，则使相应的数据块无效。 地址转换单元不同地翻译来自文件处理器的访问以及来自其他处理器的访问。

公开(公告)号：US4644490A

公开(公告)日：1987-02-17

申请号：US599167

申请日：1984-04-11

申请人： Takao Kobayashi ,  Shigeo Abe ,  Tadaaki Bandoh ,  Masao Takatoo ,  Hidekazu Matsumoto ,  Hideyuki Hara

发明人： Takao Kobayashi ,  Shigeo Abe ,  Tadaaki Bandoh ,  Masao Takatoo ,  Hidekazu Matsumoto ,  Hideyuki Hara

IPC分类号： G06F7/485 ,  G06F5/01 ,  G06F7/00 ,  G06F7/50 ,  G06F7/508 ,  G06F7/76

CPC分类号： G06F7/485 ,  G06F2207/3884

摘要： A pipelined adder for adding or subtracting two floating point input data each expressed by a sign data, an exponent data and a mantissa expressed in a sign-magnitude format, in accordance with an external operation mode designation signal to produce a floating point sum or difference data in a sign-magnitude format. In a first stage of the adder, the magnitudes of the exponent data of the input data are compared by a subtractor or a comparator and the magnitudes of the mantissa data of the input data are compared by a subtractor or a comparator. An actual operation mode for the mantissa data of the input data is determined, on the basis of the compare results of the exponent data and the mantissa data and the external operation mode designation signals, so that the operation result data is always expressed in a sign-magnitude format.

摘要翻译： 一种流水线加法器，用于根据外部操作模式指定信号，加上或减去由符号数据，指数数据和符号幅度格式表示的尾数表示的两个浮点输入数据，以产生浮点和或差 数据格式的数据。 在加法器的第一级中，通过减法器或比较器比较输入数据的指数数据的大小，并通过减法器或比较器比较输入数据的尾数数据的大小。 基于指数数据和尾数数据和外部操作模式指定信号的比较结果确定输入数据的尾数数据的实际操作模式，使得操作结果数据总是以符号表示 -magnitude格式。

公开(公告)号：US4530050A

公开(公告)日：1985-07-16

申请号：US408924

申请日：1982-08-17

申请人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Kotaro Hirasawa ,  Hidekazu Matsumoto ,  Jushi Ide ,  Takeshi Katoh ,  Hiroaki Nakanishi ,  Tetsuya Kawakami ,  Ryosei Hiraoka

发明人： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Kotaro Hirasawa ,  Hidekazu Matsumoto ,  Jushi Ide ,  Takeshi Katoh ,  Hiroaki Nakanishi ,  Tetsuya Kawakami ,  Ryosei Hiraoka

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/36

CPC分类号： G06F9/30167 ,  G06F9/30152 ,  G06F9/3016

摘要： A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.

摘要翻译： 一种用于执行可变长度指令的中央处理单元，其中用于指定操作数的寻址模式的操作数说明符与用于确定操作的种类和操作数的操作码无关。 每个操作数说明符由一个或多个数据字节形成，并且具有指示特定操作数说明符是否是最后一个操作数说明符的停止位标志。 通过添加停止位标志，可以共享操作数说明符，可以使用相同的操作码执行不同的处理。 在操作码解码装置提供指示最后一个操作数的输出的情况下，在对应的操作数说明符中没有检测到停止位平面，相应的指令被检测为错误。

公开(公告)号：US4520441A

公开(公告)日：1985-05-28

申请号：US329949

申请日：1981-12-11

申请人： Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Yasushi Fukunaga ,  Ryosei Hiraoka ,  Jushi Ide ,  Tetsuya Kawakami

发明人： Tadaaki Bandoh ,  Hidekazu Matsumoto ,  Yasushi Fukunaga ,  Ryosei Hiraoka ,  Jushi Ide ,  Tetsuya Kawakami

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/00

CPC分类号： G06F12/1027 ,  G06F12/0866

摘要： A data processing system for supporting a virtual memory is disclosed. Prior to the start of main memory write operation, a processor checks to see if a store buffer has a vacant area to store data to be written into a main memory to execute a current instruction. If a page fault occurs during the main memory write operation, the processor continues to store the subsequent write data for the current instruction and the corresponding virtual or logical addresses in the store buffer to complete execution of the current instruction.

摘要翻译： 公开了一种用于支持虚拟存储器的数据处理系统。 在主存储器写入操作开始之前，处理器检查存储缓冲器是否具有空闲区域以存储要写入主存储器中的数据以执行当前指令。 如果在主存储器写入操作期间发生页错误，则处理器继续存储当前指令的后续写入数据和存储缓冲器中的相应虚拟或逻辑地址，以完成当前指令的执行。

公开(公告)号：US5003458A

公开(公告)日：1991-03-26

申请号：US111618

申请日：1987-10-23

申请人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Takayuki Morioka ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

发明人： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Takayuki Morioka ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

IPC分类号： G06F11/14

CPC分类号： G06F11/141

摘要： Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

摘要翻译： 在微程序控制数据处理装置中进行指令重新开始处理的方法和装置，其中，在指令暂停之后重启指令执行时，指令执行暂停时的数据处理装置的内部信息被保存在存储器中，之后 暂停原因清除过程执行保存的内部信息被恢复。 根据微程序的指定，存储与当前执行的微程序地址相关联的检查点地址。 暂停之后，执行删除处理，指令的执行使用检查点地址重新开始。 如果在暂停原因移除处理被执行之后没有存储检查点地址，则从主存储器的暂停指令的读取操作重新开始指令的执行。