公开(公告)号：US5117382A

公开(公告)日：1992-05-26

申请号：US618114

申请日：1990-11-26

申请人： Hideo Maejima ,  Takashi Hotta ,  Ikuro Masuda ,  Masahiro Iwamura ,  Kouzaburou Kurita ,  Masahiro Ueno

发明人： Hideo Maejima ,  Takashi Hotta ,  Ikuro Masuda ,  Masahiro Iwamura ,  Kouzaburou Kurita ,  Masahiro Ueno

IPC分类号： G06F5/01 ,  G06F7/50 ,  G06F7/508 ,  G06F13/40 ,  G06F15/78

CPC分类号： G06F7/508 ,  G06F13/4077 ,  G06F15/7832 ,  G06F5/015 ,  G06F2207/3872 ,  Y02B60/1207 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A semiconductor integrated circuit is provided for performing an arithmetic operation using an arithmetic operation circuit. The integrated circuit includes a read bus for connecting the arithmetic operation circuit with a plurality of registers which store input data and/or output data of said arithmetic operation circuit. A precharge and sense circuit connects said arithmetic operation circuit to said read bus. The precharge and sense circuit includes a precharge circuit to precharge the read bus to a first level before the read operation, and a sense circuit to detect that the level of the read bus has discharged to a second, lower level after the read operation begins. In this way, the integrated circuit can detect very slight potential variations on said read bus.

公开(公告)号：US4789958A

公开(公告)日：1988-12-06

申请号：US703171

申请日：1985-02-19

申请人： Hideo Maejima ,  Takashi Hotta ,  Ikuro Masuda ,  Masahiro Iwamura ,  Kouzaburou Kurita ,  Masahiro Ueno

发明人： Hideo Maejima ,  Takashi Hotta ,  Ikuro Masuda ,  Masahiro Iwamura ,  Kouzaburou Kurita ,  Masahiro Ueno

IPC分类号： G06F5/01 ,  G06F7/50 ,  G06F7/508 ,  G06F13/40 ,  G06F15/78

CPC分类号： G06F7/508 ,  G06F13/4077 ,  G06F15/7832 ,  G06F5/015 ,  G06F2207/3872 ,  Y02B60/1207 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A carry-look-ahead adder is provided which is implemented as a semiconductor integrated circuit. The integrated circuit includes a bipolar transistor coupled to the output terminal for providing an output indicative of the arithmetic operation. Impedance elements are coupled to the bipolar transistor and at least one FET is provided to control the on/off state of the bipolar transistor.

摘要翻译： 提供了作为半导体集成电路实现的进位前视加法器。 集成电路包括耦合到输出端的双极晶体管，用于提供表示算术运算的输出。 阻抗元件耦合到双极晶体管，并且提供至少一个FET以控制双极晶体管的导通/截止状态。

公开(公告)号：US4727517A

公开(公告)日：1988-02-23

申请号：US785654

申请日：1985-10-09

申请人： Masahiro Ueno ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Ikuro Masuda ,  Tetsuo Nakano

发明人： Masahiro Ueno ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Ikuro Masuda ,  Tetsuo Nakano

IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C7/00

CPC分类号： G11C5/147 ,  G11C7/12

摘要： A semiconductor memory is provided including a plurality of row lines, memory cells driven by selecting a row line, sense amplifiers connected to the memory cells via column lines, and a column line voltage setting circuit for setting a predetermined voltage on the column lines. The predetermined voltage is defined by a voltage necessary to activate semiconductor switch elements constituting the column line voltage setting circuit, and is made nearly equal to the threshold voltage of the sense amplifiers. Thus, a high-speed, low power consumption semiconductor memory can be realized.

摘要翻译： 提供一种半导体存储器，其包括多条行线，通过选择行线驱动的存储单元，经由列线连接到存储单元的读出放大器，以及用于在列线上设置预定电压的列线电压设置电路。 预定电压由激活构成列线电压设定电路的半导体开关元件所需的电压限定，并且使其几乎等于读出放大器的阈值电压。 因此，可以实现高速，低功耗的半导体存储器。

公开(公告)号：US4853560A

公开(公告)日：1989-08-01

申请号：US149187

申请日：1988-01-27

申请人： Masahiro Iwamura ,  Hideo Maejima ,  Ikuro Masuda

发明人： Masahiro Iwamura ,  Hideo Maejima ,  Ikuro Masuda

IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/017545 ,  H03K19/018585 ,  H03K19/09448

摘要： When a counter-part power supply designator of a first LSI designates that the counter-part power supply voltage of another LSI is a first power supply difference which is the same as the power supply difference of its own, an output circuit control controls an output circuit and the output circuit produces an output signal having a level adaptive to the counter-part LSI operating at the first power supply voltage. When the counter-part power supply voltage designator designates that the counter-part power supply voltage difference, lower than the first power supply voltage difference, the output circuit control controls the output circuit and the output circuit produces an output signal having a level adaptive to the counter-part LSI operating at the second power supply voltage difference. Thus, a plurality of LSIs can be operated at mutually different power supply voltages.

摘要翻译： 当第一LSI的副部分电源指示符指定另一LSI的对方部分电源电压是与其自身的电源差相同的第一电源差时，输出电路控制控制输出 电路和输出电路产生具有自适应于在第一电源电压下操作的对置部分LSI的电平的输出信号。 当副部件电源电压指示符指定比第一电源电压差低的对置部分电源电压差时，输出电路控制器控制输出电路，并且输出电路产生具有自适应电平的电平的输出信号 在第二电源电压差下工作的对置部分LSI。 因此，可以在相互不同的电源电压下操作多个LSI。

公开(公告)号：US4801983A

公开(公告)日：1989-01-31

申请号：US899399

申请日：1986-08-22

申请人： Masahiro Ueno ,  Masahiro Iwamura ,  Kozaburo Kurita ,  Ikuro Masuda

发明人： Masahiro Ueno ,  Masahiro Iwamura ,  Kozaburo Kurita ,  Ikuro Masuda

IPC分类号： H03K19/0944 ,  H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H03K17/687 ,  H03K17/693 ,  H03K19/094 ,  H03K19/0952 ,  H01L27/04 ,  G11C11/40

CPC分类号： H03K17/687 ,  H01L27/0727

摘要： A unidirectional switching circuit having no charge storage effect for performing a high-speed switching operation is disclosed in which one of the anode and cathode terminals of a Schottky-barrier diode is connected to one of the source and drain terminals of a field effect transistor to form the series combination of the Schottky-barrier diode and the field effect transistor, that one of end terminals of the series combination which exists on the anode side of the diode, is used as an input terminal, the other end terminal existing on the cathode side is used as an output terminal, the gate electrode of the field effect transistor is used as a switching control electrode, and a current flowing through the switching circuit in a direction from the input terminal to the output terminal is controlled in accordance with a signal applied to the switching control electrode.

摘要翻译： 公开了一种不进行高速开关动作的电荷存储效应的单向开关电路，其中肖特基势垒二极管的阳极和阴极端子之一连接到场效应晶体管的源极和漏极端子之一， 形成肖特基势垒二极管和场效应晶体管的串联组合，存在于二极管的阳极侧的串联组合的端子之一用作输入端子，另一端子存在于阴极 侧用作输出端子，场效应晶体管的栅电极用作开关控制电极，并且根据信号控制沿着从输入端到输出端的方向流过开关电路的电流 施加到开关控制电极。

公开(公告)号：US4523276A

公开(公告)日：1985-06-11

申请号：US533803

申请日：1983-09-19

申请人： Hideo Maejima ,  Ikuro Masuda ,  Hidekazu Matsumoto ,  Shyoichi Miyazawa

发明人： Hideo Maejima ,  Ikuro Masuda ,  Hidekazu Matsumoto ,  Shyoichi Miyazawa

IPC分类号： G06F13/36 ,  G06F12/04 ,  G06F12/06 ,  G06F15/16 ,  G06F15/177 ,  G06F5/00 ,  G06F13/00

CPC分类号： G06F12/04

摘要： An input/output control device stores variable-length data in a memory device at a high storage efficiency and without reducing the speed of data processing. The data stored in a memory are read out in the form of data of a fixed word length and then processed, the data having been processed are stored in another memory in the form of data of the fixed word length. The data stored in another memory are subjected to data organization to be outputted in the form of data of a given word length. Each of the memories is divided into a plurality of regions, and each region stores therein data of the same word length, respectively.

摘要翻译： 输入/输出控制装置以高存储效率将可变长度数据存储在存储装置中，而不降低数据处理的速度。 存储在存储器中的数据以固定字长的数据的形式读出，然后被处理，已经处理的数据以固定字长的数据的形式存储在另一个存储器中。 存储在另一存储器中的数据经受数据组织以以给定字长的数据的形式输出。 每个存储器被分成多个区域，并且每个区域分别存储相同字长的数据。

公开(公告)号：US4617648A

公开(公告)日：1986-10-14

申请号：US669348

申请日：1984-11-08

申请人： Shigeo Kuboki ,  Hideo Maejima ,  Ikuro Masuda

发明人： Shigeo Kuboki ,  Hideo Maejima ,  Ikuro Masuda

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/267 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C13/00

CPC分类号： G06F11/2236 ,  G01R31/318541

摘要： A semiconductor integrated circuit device provided with a flip-flop circuit including gates which are connected to each other so as to form a closed loop, is disclosed. The device includes: first means for generating a first write timing signal, a second write timing signal, a diagnosis control signal and diagnostic data which are all concerned with the flip-flop circuit, when the device is diagnosed to detect a fault therein; second means connected to the output side of the flip-flop circuit for making and breaking the closed loop of the gates in accordance with the first write timing signal; third means connected to the output side of the flip-flop circuit for supplying the diagnostic data to the flip-flop circuit in accordance with the second write timing signal; and fourth means connected to the input side of the flip-flop circuit for blocking a signal applied to the input side of the flip-flop circuit, in accordance with the diagnosis control signal.

摘要翻译： 公开了一种半导体集成电路装置，其具备包括彼此连接形成闭环的栅极的触发电路。 所述装置包括：当所述装置被诊断为检测到其中的故障时，所述装置包括：产生第一写定时信号，第二写定时信号，诊断控制信号和全部与触发器电路有关的诊断数据的装置; 连接到所述触发器电路的输出侧的第二装置，用于根据所述第一写入定时信号使所述门的闭合环路断开; 连接到所述触发器电路的输出侧的第三装置，用于根据所述第二写定时信号将所述诊断数据提供给所述触发器电路; 以及连接到触发器电路的输入侧的第四装置，用于根据诊断控制信号阻断施加到触发器电路的输入侧的信号。

公开(公告)号：US5455955A

公开(公告)日：1995-10-03

申请号：US951772

申请日：1992-09-28

申请人： Hiroyuki Kida ,  Hideo Maejima ,  Ikuro Masuda ,  Shirou Baba

发明人： Hiroyuki Kida ,  Hideo Maejima ,  Ikuro Masuda ,  Shirou Baba

IPC分类号： G06F15/00 ,  G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/42 ,  G06F9/45 ,  G06F9/46 ,  G06F9/26 ,  G06F9/32

CPC分类号： G06F9/462 ,  G06F8/41 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30196 ,  G06F9/3814 ,  G06F9/3851 ,  G06F9/4426

摘要： A data processing system incorporating a main memory for storing instructions and operands and performing data processing in a mode of microprogram control system in response to instructions read out of the main memory. The system translates an instruction word read out of the main memory into an intermediate machine word having the orthogonal format, and addresses a microprogram memory in correspondence to the instruction word by analyzing the intermediate machine word. The system further incorporates a plurality of register sets so that each different task can use an individual register set, and a memory for memorizing the number of registers holding parameters used commonly among procedures corresponding to the register sets, so that the number of registers for each use can be changed arbitrarily for each register set by using the memory.

摘要翻译： 一种数据处理系统，包括用于存储指令和操作数的主存储器，并且响应于从主存储器读出的指令，以微程序控制系统的模式执行数据处理。 该系统将从主存储器读出的指令字转换为具有正交格式的中间机器字，并通过分析中间机器字来对应于指令字寻址微程序存储器。 该系统还包括多个寄存器组，使得每个不同的任务可以使用单个寄存器组，以及存储器，用于存储保持与寄存器组相对应的过程中共同使用的参数的寄存器的数量，使得每个寄存器的寄存器数量 通过使用存储器可以为每个寄存器设置任意使用。

公开(公告)号：US4613970A

公开(公告)日：1986-09-23

申请号：US575706

申请日：1984-01-31

申请人： Ikuro Masuda ,  Hideo Maejima ,  Terumine Hayashi ,  Kazumi Hatayama

发明人： Ikuro Masuda ,  Hideo Maejima ,  Terumine Hayashi ,  Kazumi Hatayama

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G01R15/12

CPC分类号： G01R31/318558 ,  G01R31/318516

摘要： A method of diagnosing an integrated circuit device having a plurality of combinational circuits, at least one input memory circuit connected to an input side of the combinational circuits, and an output memory circuit connected to an output side of the combinational circuits is disclosed. An input diagnostic signal is selectively applied to at least one input memory circuit connected to a given one of the combinational circuits, to read out a diagnostic signal stored in an output memory circuit connected to the given combinational circuit. Further, an integrated circuit device is disclosed which is suited to be diagnosed in the above method.

摘要翻译： 一种用于诊断具有多个组合电路的集成电路器件的方法，连接到组合电路的输入侧的至少一个输入存储器电路以及连接到组合电路的输出侧的输出存储器电路。 输入诊断信号被选择性地施加到连接到组合电路中给定的一个的至少一个输入存储器电路，以读出存储在连接到给定组合电路的输出存储器电路中的诊断信号。 此外，公开了适用于以上述方法进行诊断的集成电路装置。

公开(公告)号：US5696715A

公开(公告)日：1997-12-09

申请号：US387628

申请日：1995-02-13

申请人： Hideo Maejima ,  Ikuro Masuda

发明人： Hideo Maejima ,  Ikuro Masuda

IPC分类号： G06F15/78 ,  G11C5/06 ,  G11C7/12 ,  G11C8/06 ,  G11C17/12 ,  H01L27/02 ,  H03K19/0175 ,  H03K19/0944 ,  G11C11/407 ,  G11C11/417 ,  H03K19/01

CPC分类号： G11C17/12 ,  G06F15/786 ,  G11C5/063 ,  G11C7/12 ,  G11C8/06 ,  H01L27/0207 ,  H03K19/017518 ,  H03K19/09448

摘要： A semiconductor integrated circuit memory device has at least two logic blocks, each logic block including at least two logic units and each logic unit having a number of metal oxide semiconductor field effect transistors (MOS FET's) integrated therein. Bipolar transistors for driving the MOS FET's are selectively arranged between the logic blocks and/or the logic units so as to shorten a critical path of a logic block. The memory device may include a word driver circuit having a bipolar transistor connected to MOSFETs in an address decoder and memory cells of the memory device. The memory device may also include a sense circuit having a bipolar transistor for high speed discharge of a bit line, as well as an output buffer including a bipolar transistor for reducing signal transmission delays in driving a bus.

摘要翻译： 半导体集成电路存储器件具有至少两个逻辑块，每个逻辑块包括至少两个逻辑单元，并且每个逻辑单元具有集成在其中的多个金属氧化物半导体场效应晶体管（MOS FET）。 用于驱动MOS FET的双极晶体管被选择性地布置在逻辑块和/或逻辑单元之间，以便缩短逻辑块的关键路径。 存储器件可以包括具有连接到地址解码器中的MOSFET和存储器件的存储器单元的双极晶体管的字驱动器电路。 存储器件还可以包括具有用于位线高速放电的双极晶体管的感测电路，以及包括用于减少驱动总线中的信号传输延迟的双极晶体管的输出缓冲器。