公开(公告)号：US5804479A

公开(公告)日：1998-09-08

申请号：US694665

申请日：1996-08-09

申请人： Hideo Aoki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita ,  Takashi Hayakawa ,  Katsutoshi Matsunaga ,  Kazuhiko Saitoh ,  Michio Nishimura ,  Minoru Ohtsuka ,  Katsuo Yuhara ,  Michio Tanaka ,  Yuji Ezaki ,  Toshiyuki Kaeriyama ,  SongSu Cho

发明人： Hideo Aoki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita ,  Takashi Hayakawa ,  Katsutoshi Matsunaga ,  Kazuhiko Saitoh ,  Michio Nishimura ,  Minoru Ohtsuka ,  Katsuo Yuhara ,  Michio Tanaka ,  Yuji Ezaki ,  Toshiyuki Kaeriyama ,  SongSu Cho

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/1052 ,  H01L27/105

摘要： The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array. Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.

摘要翻译： 当通过在覆盖信息处理的上电极的BPSG膜上布置第一层布线来蚀刻和平坦化氧化硅膜时，提高作为较高海拔部分的存储器阵列的氧化硅膜的回蚀量。 仅在外围电路中存储电容元件，但不将其布置在存储器阵列中。 因此，获得具有堆叠电容器结构的DRAM，使得存储器阵列和外围电路之间的电平差减小，并且布线和连接孔的形成容易。

公开(公告)号：US5734188A

公开(公告)日：1998-03-31

申请号：US674185

申请日：1996-07-01

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

IPC分类号： H01L27/105 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L3/119

CPC分类号： H01L27/105

摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

公开(公告)号：US5732009A

公开(公告)日：1998-03-24

申请号：US685006

申请日：1996-07-22

申请人： Yoshitaka Tadaki ,  Jun Murata ,  Katsuo Yuhara ,  Yuji Ezaki ,  Michio Tanaka ,  Michio Nishimura ,  Kazuhiko Saitoh ,  Takatoshi Kakizaki ,  Shinya Nishio ,  Takeshi Sakai ,  Songsu Cho

发明人： Yoshitaka Tadaki ,  Jun Murata ,  Katsuo Yuhara ,  Yuji Ezaki ,  Michio Tanaka ,  Michio Nishimura ,  Kazuhiko Saitoh ,  Takatoshi Kakizaki ,  Shinya Nishio ,  Takeshi Sakai ,  Songsu Cho

IPC分类号： H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/02

CPC分类号： H01L27/10852 ,  H01L27/10805

摘要： A DRAM has memory cells provided at crossing points between word line conductors and bit line conductors. Each memory cell has a cell selection transistor and an information storage capacitor arranged over the bit line conductors. Unit active regions are defined in a main surface of a semiconductor substrate by a field isolation pattern. The field isolation pattern has a controlled length of extension of bird's beaks so that channel formation regions in each unit active region has almost no stepped portion to provide the cell selection transistors with a stabilized threshold voltage.

摘要翻译： DRAM具有在字线导体和位线导体之间的交叉点设置的存储单元。 每个存储单元具有单元选择晶体管和布置在位线导体上的信息存储电容器。 单元有源区通过场隔离图案限定在半导体衬底的主表面中。 场隔离图案具有可控长度的鸟嘴的延伸，使得每个单位有源区域中的沟道形成区域几乎没有阶梯部分，以向电池选择晶体管提供稳定的阈值电压。

公开(公告)号：US5684641A

公开(公告)日：1997-11-04

申请号：US570639

申请日：1995-12-11

申请人： Yasuhiro Tanaka ,  Osamu Doi ,  Kenji Inoue ,  Jun Murata ,  Michihiro Yamagata

发明人： Yasuhiro Tanaka ,  Osamu Doi ,  Kenji Inoue ,  Jun Murata ,  Michihiro Yamagata

IPC分类号： G02B13/00 ,  G02B3/06 ,  G02B13/08 ,  G11B7/125 ,  G11B7/135 ,  G02B3/02 ,  G11B7/00

CPC分类号： G02B3/06 ,  G11B7/1374 ,  G11B7/1398

摘要： In an objective lens for an optical head apparatus for reading or writing an information on a recording medium such as optical disc, astigmatism is added on axial wavefront aberration so that off-axis astigmatism is to be cancelled by the axial astigmatism. At least one surface of the objective lens is a toric or cylindrical surface, and a standard deviation of astigmatism component of axial wavefront aberration is defined as Wa is to be restricted in a range of 0

摘要翻译： 在用于在诸如光盘之类的记录介质上读取或写入信息的光学头装置的物镜中，在轴向波前像差上增加像散，使得通过轴向像散消除离轴散光。 物镜的至少一个表面是复曲面或圆柱形表面，并且将轴向波面像差的像散分量的标准偏差定义为在0

公开(公告)号：US5270768A

公开(公告)日：1993-12-14

申请号：US871547

申请日：1992-04-21

申请人： Jun Murata

发明人： Jun Murata

IPC分类号： G03G15/02 ,  G03G15/16 ,  G03G21/00

CPC分类号： G03G15/1685 ,  G03G15/0233

摘要： A charging member for use in a device, such as an electrophotographic or facsimile device, includes at least inner and outer resistance layers formed on an electrically-conductive substrate. Electrically-conductive particles dispersed in the matrix of the outer resistance layer are reduced titanium oxide which is represented by the following general formula:TiOnwhere n is a number not more than 1.9.

公开(公告)号：US5153685A

公开(公告)日：1992-10-06

申请号：US246514

申请日：1988-09-19

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided. In the sixth aspect, an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; in the seventh aspect, a refractory metal, or a refractory metal silicide QSI.sub.x, where Q is a refractory metal and 0

摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在诸如DRAM的半导体衬底之上的电容器元件。 在本发明的第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在第二方面，Y选择信号线与电容器元件的下电极层重叠。 在第三方面中，通过用于沟道阻挡区域的杂质的扩散，形成至少在电容器元件连接的开关MISFET的半导体区域下方的势垒层。 在第四方面中，电容器元件的电介质膜与其上的电容器电极层共同扩展。 在第五方面中，电容器电介质膜是其上具有氧化硅层的氮化硅膜，通过在高压下氧化氮化硅的表面层而形成氧化硅层。 在第六和第七方面中，提供了布线。 在第六方面中，在相同的真空溅射室中通过溅射形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 在第七方面中，将含有添加元素（例如Cu）的铝配线用作难熔金属或难熔金属硅化物QSIx（其中Q为难熔金属且0

公开(公告)号：US5081515A

公开(公告)日：1992-01-14

申请号：US496328

申请日：1990-03-20

申请人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

发明人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8242 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/732

CPC分类号： H01L27/10805 ,  H01L27/105

摘要： A semiconductor integrated circuit device is equipped with a DRAM whose memory cell is formed as a series circuit of a memory cell selection MISFET and a data storage capacitance element of a stacked structure. A complementary data line extends on an upper electrode layer of the data storage capacitance element of the stacked structure through an inter-level insulation film which is connected to a semiconductor region of the memory cell selection MISFET. To reduce parasitic capacitance the wiring width of the complementary data line is formed to be smaller than the film thickness of the inter-level insulation film between the complementary data line and the upper electrode layer of said data storage capacitance element of the stacked structure.

摘要翻译： 半导体集成电路器件配备有DRAM，其存储单元形成为存储单元选择MISFET和层叠结构的数据存储电容元件的串联电路。 互补数据线通过连接到存储单元选择MISFET的半导体区域的层间绝缘膜在层叠结构的数据存储电容元件的上电极层上延伸。 为了减小寄生电容，互补数据线的布线宽度形成为小于互补数据线与层叠结构的数据存储电容元件的上电极层之间的层间绝缘膜的膜厚度。

公开(公告)号：US11804055B2

公开(公告)日：2023-10-31

申请号：US17335352

申请日：2021-06-01

申请人： Jun Murata

发明人： Jun Murata

IPC分类号： G06V30/412 ,  G06V30/10

CPC分类号： G06V30/412 ,  G06V30/10

摘要： An information processing apparatus includes circuitry. The circuitry performs ledger sheet recognition on ledger sheet image data, and refers to an association information storage area storing association information representing an output order of a plurality of item values of each of a plurality of item names. The plurality of item values are acquired based on the ledger sheet recognition. The circuitry further generates output data in which the plurality of item values of the each of the plurality of item names are arranged in the output order represented by the association information. The circuitry further outputs the generated output data.

公开(公告)号：US10194031B2

公开(公告)日：2019-01-29

申请号：US15670130

申请日：2017-08-07

申请人： Yorichika Ishiyama ,  Hiroyuki Kimbara ,  Masaaki Kagawa ,  Jun Murata ,  Takahiro Yamamoto

发明人： Yorichika Ishiyama ,  Hiroyuki Kimbara ,  Masaaki Kagawa ,  Jun Murata ,  Takahiro Yamamoto

IPC分类号： H04M3/56 ,  G10L15/26 ,  G06F9/44 ,  G06N99/00 ,  G06F21/62 ,  G06F9/451 ,  H04M3/42 ,  H04M7/00

摘要： A conference assistance system and method for assisting a user in utilizing conference-related information, each of which: receives input of voice or writing of at least one meeting participant; determines whether text data representing the received voice or writing is to be used by the conference assistance system to generate assistance information, to generate a determination result; when the determination result indicates that the text data is to be used, generates, based on the text data, assistance information for assisting the meeting participant; and controls a display to display the generated assistance information.

公开(公告)号：US08983132B2

公开(公告)日：2015-03-17

申请号：US13895504

申请日：2013-05-16

申请人： Jun Murata

发明人： Jun Murata

IPC分类号： G06K9/00 ,  G06T7/00 ,  G06F17/30 ,  G06K9/46 ,  G06K9/50 ,  G06K9/48

CPC分类号： G06T7/0044 ,  G06F17/3025 ,  G06F17/30256 ,  G06F17/30259 ,  G06K9/4652 ,  G06K9/48 ,  G06K9/50

摘要： An image recognition apparatus includes a reception part that receives an image that has been read; a determination part that determines a registered object to correspond to an object included in the received image that has been read from among previously registered plural objects; a reflecting part that reflects colors of the image that has been read in previously stored plural similar objects each similar to the registered object determined by the determination part; and a printing control part that causes a printing apparatus to print the plural similar objects in which the colors have been reflected by the reflecting part.

摘要翻译： 图像识别装置包括接收已经读取的图像的接收部分; 确定部件，其确定与从先前登记的多个对象中读取的接收到的图像中包括的对象相对应的登记对象; 反映部分，反映先前存储的多个相似对象中已经读取的图像的颜色，每个类似物体类似于由确定部分确定的注册对象; 以及打印控制部，其使打印装置打印由反射部反射了颜色的多个相似物体。