公开(公告)号：US06552922B2

公开(公告)日：2003-04-22

申请号：US10228067

申请日：2002-08-27

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管，并且作为栅极电压的最小值 在板线电压升高和比较放大期间获得的晶体管的晶体管小于作为板线电压下降期间获得的晶体管中的栅极电压的最大值和比较放大的值。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US06473330B1

公开(公告)日：2002-10-29

申请号：US09585081

申请日：2000-06-01

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管，并且作为栅极电压的最小值 在板线电压升高和比较放大期间获得的晶体管的晶体管小于作为板线电压下降期间获得的晶体管中的栅极电压的最大值和比较放大的值。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US06342408B1

公开(公告)日：2002-01-29

申请号：US09658573

申请日：2000-09-08

申请人： Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

发明人： Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

IPC分类号： H01L21336

CPC分类号： G11C11/4091 ,  H01L27/10897 ,  H01L27/12

摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

摘要翻译： 半导体器件包括用作形成在绝缘膜上的衬底的半导体层，布置在半导体层上并且各自具有栅极，源极和漏极的多个MOS晶体管，多个MOS的一对MOS晶体管 构成检测电路的晶体管，用于检测施加到栅极的电位的大小，作为一对晶体管的电导率差，以及与半导体层的导电类型相同的导电类型的扩散层区域，布置在源的一部分 以及构成检测电路的一对MOS晶体管的漏极，用于将用作一对MOS晶体管的基板的部分彼此连接。

公开(公告)号：US6157997A

公开(公告)日：2000-12-05

申请号：US38834

申请日：1998-03-12

申请人： Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

发明人： Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

IPC分类号： G06F7/00 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/78

CPC分类号： G06F9/3822 ,  G06F15/7867 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/3897

摘要： Part or all of an instruction decoder is constructed of a first reconfigurable circuit wherein a circuit structure thereof can be changed according to an external signal. Further, a second reconfigurable circuit which is connected to output side of a register file as part of processing unit and wherein a circuit structure thereof can be changed according to an external signal is preliminarily provided. For special use, to achieve a predetermined operating function, the second reconfigurable circuit is reconstructed by the external signal. Further, a particular instruction corresponding to the predetermined operating function is set, and the first reconfigurable circuit is so reconstructed by an external signal that when the particular instruction is inputted, a corresponding control signal is outputted. When the particular instruction is executed, the first reconfigurable circuit outputs a control signal and the second reconfigurable circuit executes the predetermined operating function by that control signal.

摘要翻译： 指令解码器的一部分或全部由第一可重构电路构成，其中其电路结构可以根据外部信号而改变。 此外，预先提供连接到作为处理单元的一部分的寄存器堆的输出侧并且其中其电路结构可以根据外部信号改变的第二可重新配置电路。 为了特别使用，为了实现预定的操作功能，第二可重构电路由外部信号重建。 此外，设置与预定操作功能相对应的特定指令，并且通过外部信号重构第一可重新配置电路，当输入特定指令时，输出相应的控制信号。 当执行特定指令时，第一可重新配置电路输出控制信号，第二可重新配置电路通过该控制信号执行预定的操作功能。

公开(公告)号：US6130461A

公开(公告)日：2000-10-10

申请号：US291042

申请日：1999-04-14

申请人： Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

发明人： Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

IPC分类号： H01L21/8242 ,  G11C11/4091 ,  H01L27/108 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

CPC分类号： G11C11/4091 ,  H01L27/10897 ,  H01L27/12

摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

公开(公告)号：US6084453A

公开(公告)日：2000-07-04

申请号：US105959

申请日：1998-06-29

申请人： Tsuneaki Fuse ,  Masahiro Kamoshida ,  Haruki Toda ,  Yukihito Oowaki

发明人： Tsuneaki Fuse ,  Masahiro Kamoshida ,  Haruki Toda ,  Yukihito Oowaki

IPC分类号： H03K5/04 ,  G06F1/06 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03K5/156 ,  H03K7/08

CPC分类号： H03K5/1565 ,  H03K5/133

摘要： A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.

摘要翻译： 周期测量电路3测量大约是单位时间的m倍的外部时钟信号的周期。 数字转换电路5和时间转换电路7协调，产生延迟了单位时间的m / 2K倍的脉冲信号，或者是外部时钟信号的周期的1 / 2K倍。 逻辑电路8产生与外部时钟信号同步上升的内部时钟信号，并且与延迟的脉冲信号同步地下降。 因此，内部时钟信号具有与外部时钟信号相同的周期，并且具有（1 / 2K）×100％的期望占空比。

公开(公告)号：US5859805A

公开(公告)日：1999-01-12

申请号：US832818

申请日：1997-04-04

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C5/02

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

公开(公告)号：US5661678A

公开(公告)日：1997-08-26

申请号：US570966

申请日：1995-12-12

申请人： Masako Yoshida ,  Yukihito Oowaki ,  Takehiro Hasegawa ,  Kiyofumi Ochii ,  Masayuki Koizumi

发明人： Masako Yoshida ,  Yukihito Oowaki ,  Takehiro Hasegawa ,  Kiyofumi Ochii ,  Masayuki Koizumi

IPC分类号： H01L21/8242 ,  G11C11/404 ,  G11C11/405 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/404 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/10829

摘要： A semiconductor memory device comprises a memory cell array including NAND type memory cell units arranged in matrix and having a plurality of dynamic type memory cells connected in series, a plurality of word lines, a plurality of bit lines arranged within the memory cell array, the plurality of bit lines including a bit line pairs which are arranged adjacent to each other or between which at least one bit line is interposed, and a plurality of sense amplifiers of a folded bit line type, provided in each of the plurality of bit line pairs, in which the memory cells are provided in positions corresponding to intersections of the bit lines and the word lines, and complementary data are written to two memory cells connected to each of the plurality of bit line pairs and one word line, and the two memory cells store one-bit data.

摘要翻译： 半导体存储器件包括存储单元阵列，其包括以矩阵形式布置的NAND型存储单元单元，并且具有串联连接的多个动态型存储单元，多个字线，布置在存储单元阵列内的多个位线， 多个位线包括彼此相邻布置或位于其中的至少一个位线之间布置的位线对以及设置在多个位线对中的每一个中的折叠位线类型的多个读出放大器 其中存储单元被提供在与位线和字线的交点对应的位置中，并且互补数据被写入连接到多个位线对和一个字线中的每一个的两个存储器单元，并且两个存储器 单元存储一位数据。

公开(公告)号：US5644525A

公开(公告)日：1997-07-01

申请号：US272284

申请日：1994-07-08

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C5/02 ,  G11C11/407 ,  G11C11/413

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

摘要翻译： 动态半导体存储器件由沿着多个位线对排列的多个动态存储器单元和与多个位线对相关联的多个动态读出放大器组成，每个读出放大器具有连接的一对MOS晶体管 到相应的一对位线。 在一个实施例中，读出放大器之一的第一和第二晶体管和与其相邻的另一个读出放大器的第一和第二晶体管位于由两个相邻的位线对限定的区域内。 每个位线对具有在与第二方向垂直的第一方向上延伸的第一和第二位线，其中源极和漏极区域形成在半导体衬底中，使得读出放大器的晶体管每四位排列一个 线在第二个方向。

公开(公告)号：US5638329A

公开(公告)日：1997-06-10

申请号：US420079

申请日：1995-04-11

申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. AMOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

摘要翻译： MOS动态随机存取存储器包括多对位线和横向于位线的字线以定义交叉点，存储器单元阵列布置在该交叉点处。 每个单元具有存储电容器和传输门MOS晶体管，其具有耦合到字线并连接在电容器和位线之间的栅电极。 感测放大器电路连接到位线对，并且具有第一和第二公共源极线。 解码器和字线驱动器连接到字线。 AMOS晶体管连接在电源电压和第一公共源极线之间，用于选择性地向其提供潜在地限定位线对的高电平电压的第一电压。 电压发生器通过MOS晶体管连接到第二公共源极线，用于产生可能限定位线对的低电平电压的第二电压，并且被选择性地提供给第二公共源极线。 第二电压的电位比接地电位大，用作电源电压。