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1.发明授权Apparatus comprising clock control circuit, method of controlling clock signal and device using internal clock signal synchronized to external clock signal 有权装置包括时钟控制电路，控制时钟信号的方法和使用与外部时钟信号同步的内部时钟信号的装置公开(公告)号：US06473865B1
公开(公告)日：2002-10-29
申请号：US09272171
申请日：1999-03-18
IPC分类号： G06F112
CPC分类号： G06F1/3287 , G06F1/10 , G06F1/3203 , Y02D10/126 , Y02D10/171
摘要： Each delay unit is divided into two delay unit groups, the preceding stage side and the succeeding stage side. To the delay unit group in the preceding stage side, power supply voltage is supplied via a power supply terminal, and to each delay unit of the delay unit group in the succeeding stage side, power supply voltage is supplied from the power supply terminal via a power supply control switch. A forward-pulse detecting circuit detects that forward pulse was propagated to a stage between the N-th stage and a stage a predetermined number of stages before the N-th, and outputs the detected result to the power supply control switch. With this operation, when forward pulse is propagated to the (N+1)th stage, power supply voltage is supplied also to the delay unit group in the succeeding stage side. As electric power is not supplied to the delay unit group in the succeeding stage side when forward pulse is not propagated to the (N+1)th stage, wasteful consumption of electric power is prevented.
摘要翻译： 每个延迟单元被分成两个延迟单元组，即前级侧和后级侧。 对于前级侧的延迟单元组，经由电源端子向后级侧的延迟单元组的延迟单元供给电源电压，经由电源端子从电源端子供给电源电压 电源控制开关。 正向脉冲检测电路检测正向脉冲传播到第N级的第N级与预定级的级之间的级，并将检测结果输出到电源控制开关。 通过这种操作，当正向脉冲传播到第（N + 1）级时，电源电压也被提供给后级侧的延迟单元组。 当正向脉冲不传播到第（N + 1）级时，由于不向后级侧的延迟单元组提供电力，所以防止了浪费的电力消耗。
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2.发明授权Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal 有权装置包括时钟控制电路和使用与外部时钟信号同步的内部时钟信号的装置公开(公告)号：US06393080B1
公开(公告)日：2002-05-21
申请号：US09271329
申请日：1999-03-18
IPC分类号： H04L700
CPC分类号： G11C7/222 , G11C7/22 , H03K5/135 , H03L7/00 , H04L7/0337
摘要： A state-holding circuit initializing circuit initializes state-holding circuit when propagation of forward pulse to the forward-pulse delay circuits in the last stage is detected. With this operation, synchronization is established in a short time from the resumption of outputting from a receiver. The state-holding circuit control circuit also controls the reset timing of the state-holding circuit. A forward-pulse adjusting circuit controls the pulse width of forward pulse to be supplied to the forward-pulse delay line. With this operation, the stages from the stage where rearward pulse was generated to the first stage are securely turned to the set state, enabling propagation of rearward pulse and synchronization is established. Thus, synchronization is established reliably even when output from a receiver stops or the duty of an external clock signal is heavy.
摘要翻译： 状态保持电路初始化电路在正向脉冲传播到最后一级的正向脉冲延迟电路时，初始化状态保持电路。 通过该操作，从恢复从接收器输出的短时间内建立同步。 状态保持电路控制电路还控制状态保持电路的复位定时。 正向脉冲调整电路控制要提供给正向脉冲延迟线的正向脉冲的脉冲宽度。 通过该动作，从产生向后脉冲的阶段到第一阶段的阶段被牢固地转到设定状态，从而能够建立向后脉冲的传播和同步。 因此，即使从接收器的输出停止或外部时钟信号的占空比很重，也能够可靠地建立同步。
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公开(公告)号：US6084453A
公开(公告)日：2000-07-04
申请号：US105959
申请日：1998-06-29
IPC分类号： H03K5/04 , G06F1/06 , G11C11/407 , G11C11/4076 , H03K5/13 , H03K5/156 , H03K7/08
CPC分类号： H03K5/1565 , H03K5/133
摘要： A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.
摘要翻译： 周期测量电路3测量大约是单位时间的m倍的外部时钟信号的周期。 数字转换电路5和时间转换电路7协调，产生延迟了单位时间的m / 2K倍的脉冲信号，或者是外部时钟信号的周期的1 / 2K倍。 逻辑电路8产生与外部时钟信号同步上升的内部时钟信号，并且与延迟的脉冲信号同步地下降。 因此，内部时钟信号具有与外部时钟信号相同的周期，并且具有（1 / 2K）×100％的期望占空比。
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公开(公告)号：US06388484B1
公开(公告)日：2002-05-14
申请号：US09243483
申请日：1999-02-03
IPC分类号： H03L700
摘要： In this clock control circuit, clock signal CLK from a receiver is supplied to a pulse generating circuit, and the pulse generating circuit generates forward pulse, which is clock signal CLK delayed as much time as A, and pulse s which is synchronized with dock signal CLK and has a pulse width of A. Consequently, as forward pulse becomes “H” while pulse s is “L” without generating pulse which width is narrower than A, the edge part of forward pulse is securely propagated by a forward-pulse delay line even if it is high frequency. Propagation of forward pulse stops at rising edge of pulse s, and rearward pulse is generated in a corresponding stage. This rearward pulse is propagated by a rearward-pulse delay line, and outputted from an output buffer. As each delay element of forward-pulse delay line and rearward-pulse delay line is configured with one-gate circuits, propagation time of forward pulse and rearward pulse can be adjusted to the time (&tgr;−A) with high accuracy to improve synchronization accuracy.
摘要翻译： 在该时钟控制电路中，来自接收机的时钟信号CLK被提供给脉冲发生电路，并且脉冲发生电路产生正向脉冲，其是时钟信号CLK延迟多达A个时间，脉冲s与停靠信号同步 CLK并具有A的脉冲宽度。因此，当脉冲s为“L”时，正向脉冲变为“H”，而不产生宽度比A窄的脉冲，正向脉冲的边沿部分通过正向脉冲延迟可靠地传播 即使是高频也行。 正向脉冲的传播在脉冲s的上升沿停止，在相应的阶段产生向后的脉冲。 该后向脉冲由后向脉冲延迟线传播，并从输出缓冲器输出。 由于正向脉冲延迟线和后向脉冲延迟线的每个延迟元件都配置有单门电路，可以高精度地将正向脉冲和向后脉冲的传播时间调整到时间（＆Tgr--A），以提高同步性 准确性。
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公开(公告)号：US08687406B2
公开(公告)日：2014-04-01
申请号：US13597740
申请日：2012-08-29
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C13/0097 , G11C2213/71 , G11C2213/73
摘要： According to an embodiment, a semiconductor memory device comprises: a memory cell array configured having a plurality of memory cell mats, the memory cell mats including a plurality of first lines, second lines, and memory cells, and the memory cell mats being stacked such that the first and second lines are shared alternately by each of the memory cell mats; and a peripheral circuit. Each of the memory cells has a variable resistance characteristic and a current rectifying characteristic. An orientation from an anode toward a cathode of all the memory cells is identical. The peripheral circuit applies to one of the first line and the second line connected to an anode side of the selected memory cell a selected bit line voltage, and applies to the other a selected word line voltage.
摘要翻译： 根据实施例，半导体存储器件包括：配置有多个存储单元垫的存储单元阵列，所述存储单元阵列包括多个第一行，第二行和存储单元，并且存储单元阵列被堆叠 第一和第二行由每个存储单元垫交替共享; 和外围电路。 每个存储单元具有可变电阻特性和电流整流特性。 从所有存储器单元的阳极到阴极的取向是相同的。 外围电路适用于与所选存储单元的阳极侧连接的选定位线电压的第一线路和第二线路中的一条线路，并且向另一条线路电压施加。
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公开(公告)号：US20140009997A1
公开(公告)日：2014-01-09
申请号：US14005149
申请日：2012-03-07
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C2013/0073 , G11C2213/71 , G11C2213/72 , H01L27/115
摘要： A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.
摘要翻译： 一种半导体存储器件，包括存储单元阵列，所述存储单元阵列包括存储单元层，所述存储单元层包含多个用于根据不同电阻状态存储数据的存储单元; 以及访问电路，其操作以访问所述存储单元，所述存储单元在施加第一极性的电压时将所述电阻状态从第一电阻状态改变为第二电阻状态，并且从所述第二电阻状态改变所述电阻状态 在施加第二极性的电压的情况下，所述存取电路将访问所述存储单元所需的电压施加到连接到所选择的存储单元的第一和第二行，并且使所述第一和第 连接到未选择的存储器单元的第二行进入浮置状态以访问所选存储单元。
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公开(公告)号：US08537595B2
公开(公告)日：2013-09-17
申请号：US13231687
申请日：2011-09-13
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C13/02
CPC分类号： G11C8/12 , G11C13/00 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device includes: a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the selected bit line and the reference cell on the reference bit line.
摘要翻译： 一种电阻变化存储器件包括：具有层叠在其上的多层垫的单元阵列，每个垫具有彼此相交的字线和位线以及布置在其交叉处的电阻变化型存储单元，每个垫还具有 其中参考单元和连接到参考单元的参考位线，参考单元设置为一定电阻值的状态; 选择电路，被配置为选择单元阵列的每个矩阵中的字线，并且同时选择与所选择的字线和参考位线相交的位线; 以及读出放大器，被配置为通过比较所选位线上的所选存储单元和参考位线上的参考单元的各个单元电流来检测数据。
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公开(公告)号：US08400816B2
公开(公告)日：2013-03-19
申请号：US13237500
申请日：2011-09-20
申请人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
发明人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0028 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.
摘要翻译： 电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值 存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。
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公开(公告)号：US08315082B2
公开(公告)日：2012-11-20
申请号：US13446137
申请日：2012-04-13
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/0033 , G11C13/004 , G11C16/3431 , G11C2013/0047 , G11C2013/0054 , G11C2213/72
摘要： A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.
摘要翻译： 电阻变化存储器件具有存储单元的单元阵列，每个存储单元存储数据作为可逆设置的电阻值，用于从单元阵列中的选定存储单元读取数据的读出放大器，以及电压发生器电路， 在读取所选择的存储单元的数据之后，根据读取的数据，产生用于收敛该选择的存储单元的电阻状态的电压脉冲。
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公开(公告)号：US08237143B2
公开(公告)日：2012-08-07
申请号：US13217493
申请日：2011-08-25
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： H01L29/02
CPC分类号： G11C13/0004 , G11C5/02 , G11C7/18 , G11C13/0007 , G11C2211/4013 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.
摘要翻译： 存储器件具有半导体衬底; 多个单元阵列，堆叠在基板上方，每个单元阵列具有存储单元，每个通常连接沿着第一方向布置的多个单元的一端的位线和每个共同连接沿着第二方向布置的多个单元的另一端的字线; 在基板上形成的读/写电路，位于单元阵列下面; 第一和第二垂直布线沿着第一方向布置在每个单元阵列的两侧，以将位线连接到读/写电路; 以及在第二方向上设置在每个单元阵列两侧的第三垂直布线，以将字线连接到读/写电路。
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