公开(公告)号：US20140266377A1

公开(公告)日：2014-09-18

申请号：US14162297

申请日：2014-01-23

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Kareem Atout

IPC: H03K3/011

CPC classification number: H03K3/011 ,  H02M3/157 ,  H02M2001/008

Abstract: In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain.

Abstract translation: 在一个示例中，公开了一种用于电源的混合模拟 - 数字点负载控制器（ADPOL）。 ADPOL配置为响应瞬态电流负载。 在存在中等电流瞬变的情况下，功率由数字电源核心计时，数字电源核心可以被编程配置为响应于瞬态来调整脉冲宽度。 在存在较大的电流瞬变的情况下，可以将控制传递到模拟瞬态补偿器，其包括在非常高占空比时钟和非常低占空比时钟之间的高速电路选择，这将驱动瞬态回 到数字控制领域。

公开(公告)号：US20140266140A1

公开(公告)日：2014-09-18

申请号：US14205045

申请日：2014-03-11

Applicant: Analog Devices Technology

Inventor： Santiago Iriarte ,  Ramon Tortosa Navas ,  Enrique Company Bosch

IPC: G05F3/24

CPC classification number: G05F3/242 ,  G05F1/46 ,  G05F1/461 ,  G05F1/462 ,  G05F1/56 ,  G05F1/567

Abstract: A voltage generator is provided which is reliable, self starting and only requires a few components. The voltage generator comprises a first stage that provides a current to a second stage. The first stage has a temperature coefficient of one sign, such as positive, and the second stage has an opposing temperature coefficient, e.g. negative. The responses are summed such that the overall temperature coefficient is reduced.

Abstract translation: 提供电压发生器，可靠，自启动，只需要几个部件。 电压发生器包括向第二级提供电流的第一级。 第一阶段具有一个符号的温度系数，例如正的，第二阶段具有相反的温度系数，例如。 负。 将响应相加，使得总体温度系数降低。

公开(公告)号：US20140254991A1

公开(公告)日：2014-09-11

申请号：US13787362

申请日：2013-03-06

Applicant: Bernhard STRZALKOWSKI

Inventor： Bernhard STRZALKOWSKI

IPC: G02B6/43

CPC classification number: G02B6/43 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2924/00014

Abstract: An isolator comprising: a first semiconductor substrate including a first electrical circuit; a second semiconductor substrate including a second electrical circuit; and at least one optical waveguide for data exchange between the first and second electrical circuits.

Abstract translation: 一种隔离器，包括：包括第一电路的第一半导体衬底; 包括第二电路的第二半导体衬底; 以及用于在第一和第二电路之间进行数据交换的至少一个光波导。

公开(公告)号：US20140253061A1

公开(公告)日：2014-09-11

申请号：US13789210

申请日：2013-03-07

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Shanshan Yang ,  Guoming Wu ,  Bin Shao

IPC: G05F1/46

CPC classification number: G05F1/46 ,  H02M1/36 ,  H02M3/158 ,  H02M2001/0032 ,  Y02B70/16

Abstract: A method and system to inhibit the switching of a current mode switching converter having high and low side switching elements coupled to an output inductor, the other end of which is coupled to an output node, and operated with respective modulated switching signals to regulate an output voltage Vout produced at the node. A current IC that varies with the difference between a reference voltage and a voltage proportional to Vout is compared with and a current IDETECT—PEAK which varies with the current conducted by the high side switching element; the result of the comparison of IC and IDETECT—PEAK is used to control the regulation of Vout during normal operation. Current IC is also compared with a current IDETECT—VALLEY which varies with the current conducted by the low side switching element. When IDETECT—VALLEY>IC, a ‘skip mode’ is triggered during which the switching signals are inhibited.

Abstract translation: 一种抑制具有耦合到输出电感器的高低侧开关元件的电流模式切换转换器的方法和系统，该输出电感器的另一端耦合到输出节点，并且用相应的调制开关信号进行操作，以调节输出 在节点处产生的电压Vout。 与参考电压和与Vout成比例的电压之间的差异变化的电流IC与当前由高侧开关元件传导的电流变化的IDETECT-PEAK进行比较; IC和IDETECT-PEAK的比较结果用于控制正常工作期间Vout的调节。 电流IC还与当前的IDETECT-VALLEY进行比较，其随着低侧开关元件所传导的电流而变化。 当IDETECT-VALLEY> IC时，触发切换信号的“跳过模式”。

公开(公告)号：US08760201B1

公开(公告)日：2014-06-24

申请号：US13793438

申请日：2013-03-11

Applicant: Analog Devices Technology

Inventor： Ting Gao ,  Jiefeng Yan

IPC: H03L7/06

CPC classification number: H03L7/0895

Abstract: Systems and methods for capacitance multiplication using one charge pump for a phase lock loop employ a digital controlled loop filter that operates in a time division mode. Embodiments of the loop filter block the current from the charge pump according to the digital control, such that the charge pump cannot charge or discharge the integral capacitor when the digital control is enabled. Because at least a portion of the current is blocked, it takes more time for the charge pump to charge or discharge the capacitor to a certain level. The capacitor then appears to be larger than its actual value with respect to operation of the phase lock loop.

Abstract translation: 使用一个用于锁相环的电荷泵进行电容倍增的系统和方法采用以时分模式工作的数字控制环路滤波器。 环路滤波器的实施例根据数字控制阻挡来自电荷泵的电流，使得当数字控制被使能时，电荷泵不能对积分电容器充电或放电。 因为电流的至少一部分被阻塞，所以电荷泵将电容器充电或放电到一定水平需要更多的时间。 相对于锁相环的操作，电容器似乎大于其实际值。

公开(公告)号：US20140115301A1

公开(公告)日：2014-04-24

申请号：US13738858

申请日：2013-01-10

Applicant: Kaushal Sanghai ,  Michael G. Perkins ,  Andrew J. Higham

Inventor： Kaushal Sanghai ,  Michael G. Perkins ,  Andrew J. Higham

IPC: G06F9/38

CPC classification number: G06F9/30018 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/3012 ,  G06F9/325 ,  G06F9/3887

Abstract: The present disclosure provides a processor, and associated method, for performing parallel processing within a register. An exemplary processor may include a processing element having a compute unit and a register file. The register file includes a register that is divisible into lanes for parallel processing. The processor may further include a mask register and a predicate register. The mask register and the predicate register respective include a number of mask bits and predicate bits equal to a maximum number of divisible lanes of the register. A state of the mask bits and predicate bits is set to respectively achieve enabling/disabling of the lanes from executing an instruction and conditional performance of an operation defined by the instruction. Further, the processor is operable to perform a reduction operation across the lanes of the processing element and/or generate an address for each of the lanes of the processing element.

Abstract translation: 本公开提供了一种用于在寄存器内执行并行处理的处理器和相关联的方法。 示例性处理器可以包括具有计算单元和寄存器文件的处理元件。 寄存器文件包括可以划分为并行处理通道的寄存器。 处理器还可以包括掩码寄存器和谓词寄存器。 掩模寄存器和谓词寄存器分别包括等于寄存器的可分割通道的最大数目的掩码位和谓词位数。 将掩码位和谓词位的状态设置为分别执行指令的执行/禁止，以及由指令定义的操作的条件执行。 此外，处理器可操作以在处理元件的通道上执行缩减操作和/或为处理元件的每个通道生成地址。

公开(公告)号：US20140074901A1

公开(公告)日：2014-03-13

申请号：US14055177

申请日：2013-10-16

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andreas D. Olofsson ,  Baruch Yanovitch

IPC: G06F17/10

CPC classification number: G06F17/10 ,  G06F7/5324 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3885

Abstract: Multiplication engines and multiplication methods are provided for a digital processor. A multiplication engine includes multipliers, each receiving a first operand and a second operand; a local operand register having locations to hold the first operands for respective multipliers; a first operand bus coupled to the local operand register to supply the first operands from a compute register file to the local operand register; a second operand bus coupled to the plurality of multipliers to supply one or more of to the second operands from the compute register file to respective multipliers; and a control unit responsive to a digital processor instruction to supply the first operands from the local operand register to respective multipliers, to supply the second operands from the compute register file to respective multipliers on the second operand bus and to multiply the first operands by the respective second operands in the respective multipliers, wherein one or more of the first operands in the local operand register are reused by the multipliers in two or more multiplication operations.

Abstract translation: 为数字处理器提供乘法引擎和乘法方法。 乘法引擎包括乘法器，每个乘法器接收第一操作数和第二操作数; 本地操作数寄存器，其具有用于保持各乘法器的第一操作数的位置; 耦合到本地操作数寄存器的第一操作数总线，用于将第一操作数从计算寄存器文件提供给本地操作数寄存器; 耦合到所述多个乘法器的第二操作数总线，以将所述第二操作数中的一个或多个从计算寄存器文件提供给各个乘法器; 以及控制单元，其响应于数字处理器指令将第一操作数从本地操作数寄存器提供给各个乘法器，以将第二操作数从计算寄存器文件提供给第二操作数总线上的相应乘法器，并将第一操作数乘以 各个乘法器中的相应的第二操作数，其中本地操作数寄存器中的第一操作数中的一个或多个在两个或多个乘法运算中由乘法器重新使用。

公开(公告)号：US20130292793A1

公开(公告)日：2013-11-07

申请号：US13740677

申请日：2013-01-14

Applicant: Patrick F. M. POUCHER ,  Padraig L. FITZGERALD ,  John Jude O'DONNELL ,  Oliver J. KIERSE ,  Denis M. O'CONNOR

Inventor： Patrick F. M. POUCHER ,  Padraig L. FITZGERALD ,  John Jude O'DONNELL ,  Oliver J. KIERSE ,  Denis M. O'CONNOR

IPC: H01L29/06 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L23/16 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit may include a semiconductor die having a trench formed in a surface of the semiconductor die. One or more circuit components may be formed on the surface of the semiconductor die. The trench can extend into the semiconductor die next to at least one circuit component. The trench may surround the circuit component partially or wholly. The trench may be filled with a material having a lower bulk modulus than the semiconductor die in which the trench is formed.

Abstract translation: 集成电路可以包括具有形成在半导体管芯的表面中的沟槽的半导体管芯。 可以在半导体管芯的表面上形成一个或多个电路部件。 沟槽可以延伸到半导体管芯中，靠近至少一个电路部件。 沟槽可以部分或全部地围绕电路部件。 沟槽可以填充具有比其中形成沟槽的半导体管芯更低的体积模量的材料。

公开(公告)号：US09755602B2

公开(公告)日：2017-09-05

申请号：US14258634

申请日：2014-04-22

Applicant: Analog Devices Technology ,  Analog Devices, Inc.

Inventor： Eberhard Brunner ,  Jeff Venuti

IPC: H04B1/04 ,  H03G3/30 ,  H03F3/19 ,  H03F3/45 ,  H03G1/00 ,  H03C1/62

CPC classification number: H03G3/3042 ,  H03F3/19 ,  H03F3/4508 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/45116 ,  H03F2203/45154 ,  H03F2203/45306 ,  H03G1/0023

Abstract: A system has a baseband gain stage to receive incoming in-phase and quadrature voltage signals and output in-phase and quadrature current signals, a mixer core arranged to receive the in-phase and quadrature current signals and output radio frequency signals, and a variable gain amplifier to receive the radio frequency signals and produce a broadband radio signal.

公开(公告)号：US20160094240A1

公开(公告)日：2016-03-31

申请号：US14496980

申请日：2014-09-25

Applicant: Anthony Evan O'Shaughnessy ,  Colin Lyden ,  Joseph Peter Canning

Inventor： Anthony Evan O'Shaughnessy ,  Colin Lyden ,  Joseph Peter Canning

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03H17/0621 ,  H03H17/0642 ,  H03H17/0664 ,  H03H17/0685

Abstract: It is known to perform sample rate conversion. A sample rate converter is arranged to receive digital data at an input sample rate Fs and to output data at an output sample rate Fo, where Fo=Fs/N, and N is decimation factor greater than 1. A problem can arise with sample rate converters when a user wishes to change the decimation rate. Generally a sample rate converter needs to discard the samples in its filter when the decimation rate is changed, and the filter output is unusable until the filter has refilled with values taken at the new decimation rate. The sample rate converter provided here does not suffer from this problem. The sample rate converter includes at least Q channels. Each channel comprises a Qth order filter arranged to select input signals at predetermined intervals from a run of P input signals, and to form a weighted sum of the selected input signals to generate an output value, and where the runs of P input signals of one channel are offset from the runs of P signals of the other channels.

Abstract translation: 已知进行采样率转换。 采样率转换器被布置为以输入采样率Fs接收数字数据，并以输出采样率Fo输出数据，其中Fo = Fs / N，N是抽取因子大于1.可能会出现采样率的问题 转换器，当用户希望改变抽取率时。 通常，抽样速率改变时，采样率转换器需要丢弃其滤波器中的样本，并且滤波器输出不可用，直到滤波器用新的抽取率取值为止。 这里提供的采样率转换器不会受到这个问题的困扰。 采样率转换器至少包括Q个通道。 每个通道包括Q阶滤波器，其布置成从P个输入信号的行程中以预定间隔选择输入信号，并且形成所选输入信号的加权和以产生输出值，并且其中一个P输入信号的运行 通道偏离其他通道的P信号的运行。