公开(公告)号：US20140002468A1

公开(公告)日：2014-01-02

申请号：US13897332

申请日：2013-05-17

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Si-Duk Sung

IPC: G09G5/399 ,  G09G5/14 ,  G09G3/32

CPC classification number: G09G5/399 ,  G09G3/003 ,  G09G3/2022 ,  G09G3/3208 ,  G09G5/14 ,  G09G2300/0452 ,  G09G2300/0857 ,  G09G2310/0224

Abstract: The present invention relates to a memory, a memory addressing method, and a display device. The memory stores first image data and second image data of a line unit stored in a line buffer unit. The memory includes at least a first DDR3 memory and a second DDR3 memory, reads the first image data of the line unit, divides the read first image data of the line unit, and writes the divided data to a corresponding block among a plurality of blocks of each of the first DDR3 memory and the second DDR3 memory. Also, the memory reads second image data of the line unit, divides the read second image data of the line unit, and writes the divided data to another corresponding block among the plurality of blocks of each of the first DDR3 memory and the second DDR3 memory.

Abstract translation: 本发明涉及存储器，存储器寻址方法和显示装置。 存储器存储存储在行缓冲单元中的行单元的第一图像数据和第二图像数据。 存储器至少包括第一DDR3存储器和第二DDR3存储器，读取线路单元的第一图像数据，划分线单元的读取的第一图像数据，并将划分的数据写入多个块中的相应块 的第一个DDR3内存和第二个DDR3内存。 此外，存储器读取线路单元的第二图像数据，划分线单元的读取的第二图像数据，并将划分的数据写入到第一DDR3存储器和第二DDR3存储器中的每一个的多个块中的另一对应块 。

公开(公告)号：US08576257B2

公开(公告)日：2013-11-05

申请号：US12339742

申请日：2008-12-19

Applicant: Hiroshi Kiya ,  Chihiro Shin ,  Haruo Kamijo ,  Motoaki Nishimura ,  Katsuhiko Maki

Inventor： Hiroshi Kiya ,  Chihiro Shin ,  Haruo Kamijo ,  Motoaki Nishimura ,  Katsuhiko Maki

IPC: G09G5/10

CPC classification number: G09G3/3685 ,  G09G3/2007 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2300/0857 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2310/0294 ,  G09G2330/028 ,  G09G2370/08

Abstract: An integrated circuit device includes first to Nth memory blocks disposed along a first direction, a power supply circuit, and a data driver disposed in a second direction with respect to the first to Nth memory blocks. The power supply circuit includes an analog reference power supply voltage output circuit that outputs an analog reference power supply voltage. The analog reference power supply voltage output circuit is disposed between an Mth memory block and an (M+1)th memory block among the first to Nth memory blocks. An analog reference power supply line is provided in an area of the data driver along the first direction.

Abstract translation: 集成电路装置包括沿着第一方向布置的第一至第N存储块，电源电路和与第一至第N存储器块相对的第二方向的数据驱动器。 电源电路包括输出模拟基准电源电压的模拟基准电源电压输出电路。 模拟基准电源电压输出电路设置在第一至第N存储块之间的第M个存储块和第（M + 1）个存储器块之间。 在数据驱动器的沿着第一方向的区域中提供模拟参考电源线。

公开(公告)号：US20130257846A1

公开(公告)日：2013-10-03

申请号：US13993922

申请日：2011-12-12

Applicant: Eiji Matsuda ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Seijirou Gyouten ,  Shuji Nishi ,  Makoto Yokoyama

Inventor： Eiji Matsuda ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Seijirou Gyouten ,  Shuji Nishi ,  Makoto Yokoyama

IPC: G09G3/36

CPC classification number: G09G3/3618 ,  G09G3/3648 ,  G09G2300/0852 ,  G09G2300/0857 ,  G09G2300/0876

Abstract: A memory-type liquid crystal display device includes transistors (N1, N2), retention electrodes (MRY), refresh output control sections (RS1), and capacitors (Cb1). In a data retention period, an electric potential of each of the retention electrodes (MRY) is changed via a corresponding one of the capacitors (Cb1) by changing an electric potential level of a retention capacitor wire signal that is supplied to a corresponding CS line (CSL(i)). Each of the refresh output control sections (RS1) receives the electric potential thus changed of a corresponding one of the retention electrodes (MRY) via the input section and controls an electric potential of a corresponding pixel electrode (PIX) in accordance with the electric potential thus changed.

Abstract translation: 记忆型液晶显示装置包括晶体管（N1，N2），保持电极（MRY），刷新输出控制部分（RS1）和电容器（Cb1）。 在数据保持期间，通过改变提供给相应的CS行的保持电容配线信号的电位电平，经由相应的一个电容器（Cb1）来改变每个保持电极（MRY）的电位 （CSL（i））。 每个刷新输出控制部分（RS1）经由输入部分接收相应的一个保持电极（MRY）所改变的电位，并根据电位控制对应的像素电极（PIX）的电位 从而改变了。

公开(公告)号：US08537103B2

公开(公告)日：2013-09-17

申请号：US12472400

申请日：2009-05-27

Applicant: Jun Koyama

Inventor： Jun Koyama

IPC: G09G3/34

CPC classification number: G09G3/344 ,  G09G3/2074 ,  G09G2300/08 ,  G09G2300/0809 ,  G09G2300/0857 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2330/021

Abstract: An object of the present invention is to provide an active matrix type electrophoresis display device whose number of the times of writings is further smaller. In an electrophoresis display device which performs the display of picture using a n-bit digital picture signal, the respective pixels are divided into a plurality of sub-pixels, the respective sub-pixels have a 1-bit memory circuit. Since an electrophoresis element is stable in once written state, upon the display of static picture, the picture is retained by the digital picture signal retained in a memory circuit, therefore, a periodic refresh operation which is conventionally considered to be required are capable of being omitted.

公开(公告)号：US08482496B2

公开(公告)日：2013-07-09

申请号：US11811842

申请日：2007-06-12

Applicant: Stephen R. Lewis

Inventor： Stephen R. Lewis

IPC: G09G3/34

CPC classification number: G09G3/3433 ,  G09G3/2022 ,  G09G3/2081 ,  G09G3/3406 ,  G09G3/3466 ,  G09G2300/0473 ,  G09G2300/08 ,  G09G2300/0809 ,  G09G2300/0857 ,  G09G2310/02 ,  G09G2310/0262 ,  G09G2310/063

Abstract: The invention relates to methods and apparatus for forming images on a display utilizing a control matrix to control the movement of MEMs-based light modulators.

Abstract translation: 本发明涉及利用控制矩阵在显示器上形成图像以控制基于MEM的光调制器的移动的方法和装置。

公开(公告)号：US08450121B2

公开(公告)日：2013-05-28

申请号：US13240436

申请日：2011-09-22

Applicant: Kyung-hoon Chung

Inventor： Kyung-hoon Chung

IPC: H01L51/56

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0857 ,  G09G2300/0861 ,  G09G2320/0295

Abstract: A pixel includes an organic light emitting diode, a first transistor having a source coupled to a first power source, a control gate coupled to a first node, and a drain coupled to a second node, wherein the first transistor includes a floating gate and an insulating layer between the floating gate and the control gate, a second transistor having a source coupled to a data line, a drain coupled to the first node, and a gate coupled to a scan line, a third transistor having a source coupled to the second node, a drain coupled to the organic light emitting diode, and a gate coupled to one of a light emitting control line and the scan line, and a capacitor coupled between the first power source and the first node.

Abstract translation: 像素包括有机发光二极管，具有耦合到第一电源的源极的第一晶体管，耦合到第一节点的控制栅极和耦合到第二节点的漏极，其中所述第一晶体管包括浮置栅极和 在浮置栅极和控制栅极之间的绝缘层，具有耦合到数据线的源极的第二晶体管，耦合到第一节点的漏极和耦合到扫描线的栅极，第三晶体管，具有耦合到第二晶体管的源极 耦合到有机发光二极管的漏极，以及耦合到发光控制线和扫描线之一的栅极以及耦合在第一电源和第一节点之间的电容器。

公开(公告)号：US20130106816A1

公开(公告)日：2013-05-02

申请号：US13287742

申请日：2011-11-02

Applicant: Peter Lapidus ,  Michael Yee ,  Bruce C. Gamache

Inventor： Peter Lapidus ,  Michael Yee ,  Bruce C. Gamache

IPC: G09G5/00

CPC classification number: G09G3/3651 ,  G09G3/2025 ,  G09G2300/0857 ,  G09G2310/0235

Abstract: A controller and method have been described for use in conjunction with a sequential display system including a display having a plurality of pixels. A series of update cycles is performed on the display to establish the grayscale value of each pixel for viewing a given frame using the display during which update cycles each pixel can have a single update to change states and without refreshing an existing state of the pixel.

Abstract translation: 已经描述了与包括具有多个像素的显示器的顺序显示系统结合使用的控制器和方法。 在显示器上执行一系列更新周期以建立用于使用显示器观看给定帧的每个像素的灰度值，在该显示期间，更新周期，每个像素可以具有单个更新以改变状态并且不刷新像素的现有状态。

公开(公告)号：US08421807B2

公开(公告)日：2013-04-16

申请号：US12793327

申请日：2010-06-03

Applicant: Keitaro Yamashita

Inventor： Keitaro Yamashita

IPC: G09F15/00 ,  G09G3/36

CPC classification number: G09G3/3666 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2300/0842 ,  G09G2300/0857 ,  G09G2310/0218 ,  G09G2310/08 ,  G09G2330/025

Abstract: A display device includes a display unit and a plurality of refreshing units. The display unit has a plurality of the display areas. Each of the display areas has a plurality of pixels. Each of the pixels has a memory. The refreshing units respectively control to refresh the pixels of the corresponding display areas at different time periods. Thus, the produced peak current during the pixel refreshing can be reduced, and the stored pixel data can be maintained.

Abstract translation: 显示装置包括显示单元和多个刷新单元。 显示单元具有多个显示区域。 每个显示区域具有多个像素。 每个像素都有一个内存。 刷新单元分别控制在不同时间段刷新相应显示区域的像素。 因此，可以减少在像素刷新期间产生的峰值电流，并且可以保持存储的像素数据。

公开(公告)号：US08390565B2

公开(公告)日：2013-03-05

申请号：US12463467

申请日：2009-05-11

Applicant: Tetsuro Murayama ,  Yasuhiro Shimodaira ,  Hiroshi Maeda

Inventor： Tetsuro Murayama ,  Yasuhiro Shimodaira ,  Hiroshi Maeda

IPC: G09G3/34

CPC classification number: G02F1/167 ,  G09G3/2074 ,  G09G3/344 ,  G09G2300/0443 ,  G09G2300/0814 ,  G09G2300/0857 ,  G09G2310/0262 ,  G09G2310/04 ,  G09G2320/0209 ,  G09G2320/043 ,  G09G2330/021

Abstract: An electrophoretic display device includes a first substrate and a second substrate that face each other, an electrophoretic element disposed between the first substrate and the second substrate, the electrophoretic element including electrophoretic particles, a display unit that has a plurality of pixels including the electrophoretic element, a common electrode that is formed on an electrophoretic element side of the second substrate, and a first control line and a second control line that are formed in either the first substrate or the second substrate. Each of the plurality of pixels includes a pixel switching element, a memory circuit that is connected to the pixel switching element, a switching circuit that is connected to the memory circuit, and a first pixel electrode and a second pixel electrode that are connected to the switching circuit and are disposed to face the common electrode. The switching circuit includes a first switch that controls a conductive state between the first control line and the first pixel electrode in accordance with an output signal of the memory circuit and a second switch that controls a conductive state between the second control line and the second pixel electrode in accordance with the output signal of the memory circuit.

Abstract translation: 电泳显示装置包括彼此相对的第一基板和第二基板，设置在第一基板和第二基板之间的电泳元件，电泳元件包括电泳粒子，显示单元，其具有包括电泳元件的多个像素 形成在第二基板的电泳元件侧的公共电极，以及形成在第一基板或第二基板中的第一控制线和第二控制线。 多个像素中的每个像素包括像素开关元件，连接到像素开关元件的存储电路，连接到存储电路的开关电路和连接到存储电路的第一像素电极和第二像素电极 并且被设置为面对公共电极。 开关电路包括：第一开关，其根据存储电路的输出信号控制第一控制线与第一像素电极之间的导通状态，第二开关控制第二控制线与第二像素之间的导通状态 电极根据存储电路的输出信号。

公开(公告)号：US08339351B2

公开(公告)日：2012-12-25

申请号：US12490469

申请日：2009-06-24

Applicant: Kozo Yasuda

Inventor： Kozo Yasuda

IPC: G09G3/36

CPC classification number: G09G3/3659 ,  G02F1/13624 ,  G09G3/3614 ,  G09G2300/0823 ,  G09G2300/0857 ,  G09G2330/021

Abstract: A display device includes a memory unit formed in each pixel to store video data and including a first inverter circuit whose input terminal is connected to a first node and whose output terminal is connected to a second node and a second inverter circuit whose input terminal is connected to the second node and whose output terminal is connected to the first node, a first transistor connected between the output terminal of the second inverter circuit and the video line, and a second transistor connected between the first node and the video line, in which at the time of reading the video data, the first transistor is turned ON, and the second transistor is turned OFF, to output the video data stored in the memory unit to the video line.

Abstract translation: 显示装置包括形成在每个像素中的存储单元以存储视频数据，并且包括其输入端连接到第一节点并且其输出端连接到第二节点的第一反相器电路和输入端连接的第二反相器电路 连接到第二节点并且其输出端子连接到第一节点，连接在第二反相器电路的输出端子和视频线之间的第一晶体管和连接在第一节点和视频线路之间的第二晶体管，其中， 读取视频数据的时间，第一晶体管导通，第二晶体管截止，将存储在存储单元中的视频数据输出到视频线。