公开(公告)号：US20110182102A1

公开(公告)日：2011-07-28

申请号：US12730089

申请日：2010-03-23

申请人： Yoshihiro MINAMI

发明人： Yoshihiro MINAMI

IPC分类号： G11C11/22 ,  G11C7/00

CPC分类号： H01L21/84 ,  G11C11/22 ,  G11C11/223 ,  G11C11/5657 ,  G11C2211/562 ,  G11C2211/5648 ,  H01L27/10802 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

摘要： A memory includes memory cells on a semiconductor layer, in which each of the memory cells includes a source layer and a drain layer in the semiconductor layer; an electrically floating body region provided in the semiconductor layer between the source layer and the drain layer and configured to accumulate or discharge electric charges in order to store logical data; a gate dielectric film provided on the body region and comprising a ferroelectric film with polarization characteristics; and a gate electrode provided on the gate dielectric film above the body region, wherein each memory cell stores a plurality of logical data depending on an amount of electric charges accumulated in the body region and on a polarization state of the ferroelectric film.

摘要翻译： 存储器包括半导体层上的存储单元，其中每个存储单元包括半导体层中的源极层和漏极层; 电浮置体区域，设置在所述源极层和漏极层之间的所述半导体层中，并且被配置为积累或放电电荷以便存储逻辑数据; 设置在所述本体区域上并具有极化特性的铁电体膜的栅极电介质膜; 以及设置在所述体区域上方的所述栅极电介质膜上的栅电极，其中，每个存储单元根据所述体区中累积的电荷量和所述强电介质膜的极化状态来存储多个逻辑数据。

公开(公告)号：US07986554B2

公开(公告)日：2011-07-26

申请号：US12051492

申请日：2008-03-19

申请人： Yan Li

发明人： Yan Li

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C2211/5648

摘要： For a non-volatile memory storing three or more bits per cell, pages of data are written in an order where more than one, but less than all of the logical pages that a physical page along a wordline can store are written concurrently. More than one, but less than all of the logical pages that a physical page along a wordline can store are then written concurrently on an adjacent wordline. The process then comes back to the first wordline and writes at least one more logical page. A process is also described where one or more logical pages are written into a physical page along a wordline, after which one or more logical pages are written into a physical page along an adjacent wordline. A read operation is then performed on the first wordline and the resultant read is corrected based on the result of programming the adjacent wordline. This corrected read is then used in writing at least one more logical page in a second programming operation on the first wordline.

摘要翻译： 对于每个单元存储三个或更多位的非易失性存储器，以与字线一起的物理页面可以存储的所有逻辑页面多于一个但是小于同时写入的所有逻辑页面的顺序写入数据页。 但是，一个字面上可以存储的物理页面上的所有逻辑页面都可以同时写在相邻的字线上。 然后，该过程返回到第一个字线，并写入至少一个逻辑页面。 还描述了一个过程，其中一个或多个逻辑页面沿着字线被写入物理页面，之后将一个或多个逻辑页面沿着相邻字线写入物理页面。 然后对第一字线执行读取操作，并且基于相邻字线的编程结果校正所得到的读取。 然后，在第一字线上的第二编程操作中，将该校正后的读取写入至少一个逻辑页面。

公开(公告)号：US07885107B2

公开(公告)日：2011-02-08

申请号：US12219663

申请日：2008-07-25

申请人： Ju-hee Park ,  Young-moon Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song

发明人： Ju-hee Park ,  Young-moon Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5648

摘要： A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed by setting the threshold voltage to a second voltage level based on a value of the second bit. The second voltage level is the same as the first voltage level if the second bit is a first value and the second voltage level is within a second of the plurality of threshold voltage distributions if the second bit is a second value. A third bit of the multi-bit data is programmed by setting the threshold voltage to a third voltage level based on a value of the third bit.

摘要翻译： 一种编程非易失性存储单元的方法包括通过将非易失性存储单元的阈值电压设置为多个阈值电压分布中的第一个内的第一电压电平来对第一位多位数据进行编程。 通过基于第二位的值将阈值电压设置为第二电压电平来编程多位数据的第二位。 如果第二位是第二值，则第二电压电平与第一电压电平相同，如果第二位是第二值，则第二电压电平在多个阈值电压分布的一秒内。 通过将阈值电压设置为基于第三位的值的第三电压电平来编程多位数据的第三位。

公开(公告)号：US20100277980A1

公开(公告)日：2010-11-04

申请号：US12837595

申请日：2010-07-16

申请人： Noboru SHIBATA ,  Tomoharu TANAKA

发明人： Noboru SHIBATA ,  Tomoharu TANAKA

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5646 ,  G11C2211/5648 ,  G11C2216/14

摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.

摘要翻译： 数据存储电路以一一对应的方式连接到位线。 写电路将第一页上的数据写入由字线同时选择的多个第一存储单元。 此后，写电路将第二页上的数据写入多个第一存储单元。 然后，写入电路将第一和第二页面上的数据写入与位线方向相邻的第一存储单元的第二存储单元。

公开(公告)号：US20100103733A1

公开(公告)日：2010-04-29

申请号：US12427007

申请日：2009-04-21

申请人： Gerrit Jan Hemink

发明人： Gerrit Jan Hemink

IPC分类号： G11C16/02 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3468 ,  G11C16/3486 ,  G11C2211/5621 ,  G11C2211/5648

摘要： Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of the non-volatile storage elements to a set of target conditions using programming pulses. For at least a subset of the programming processes, a programming pulse associated with achieving an intermediate result for a respective programming process is identified, a pulse increment between programming pulses is decreased for the respective programming process while continuing the respective programming process to program non-volatile storage elements to the respective one or more targets and the identified programming pulse is used to adjust a starting programming voltage for a subsequent programming process.

摘要翻译： 对多个非易失性存储元件执行多个编程处理。 编程过程中的每一个操作以使用编程脉冲将至少一个非易失性存储元件的子集编程到一组目标条件。 对于编程过程的至少一个子集，识别与实现相应编程处理的中间结果相关联的编程脉冲，针对相应的编程过程减少编程脉冲之间的脉冲增量，同时继续相应的编程处理， 易失性存储元件到相应的一个或多个目标，并且所识别的编程脉冲用于调整用于后续编程处理的起始编程电压。

公开(公告)号：US07668012B2

公开(公告)日：2010-02-23

申请号：US11932096

申请日：2007-10-31

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5648

摘要： One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states. Such embodiments include programming, separately, the first cell to one of a third number of states based, at least in part, on the one of the first number of states and the second cell to one of a fourth number of states based, at least in part, on the one of the second number of states.

摘要翻译： 一个或多个实施例包括并行地将第一小区编程为第一数量状态中的一个，将第二小区编程为第二数量的状态中的一个。 这样的实施例包括至少部分地基于至少一个状态的第一数量状态和第二小区中的一个至第四数量的状态来将第一小区单独地编程为第三数量的状态中的一个 部分地是第二个国家之一。

公开(公告)号：US20090129152A1

公开(公告)日：2009-05-21

申请号：US11943772

申请日：2007-11-21

申请人： Frankie F. Roohparvar

发明人： Frankie F. Roohparvar

IPC分类号： G11C11/34

CPC分类号： G06F13/4239 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C27/005 ,  G11C2211/5648 ,  H04N9/78

摘要： Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Program and read operations are performed in opposite directions to allow for subtraction of impact of subsequently programmed cells on target cells being read.

摘要翻译： 适于处理和产生表示两个或更多位信息的数据值的模拟数据信号的存储器件有助于相对于器件处理和仅产生指示各个位的二进制数据信号的数据传输速率的增加。 这种存储器件的编程包括编程到表示所需位图案的目标阈值电压范围。 读取这样的存储器件包括产生指示目标存储器单元的阈值电压的模拟数据信号。 程序和读取操作在相反的方向上进行，以便减少随后编程的单元对被读取的目标单元的影响。

公开(公告)号：US07529129B2

公开(公告)日：2009-05-05

申请号：US12035552

申请日：2008-02-22

申请人： Frankie F. Roohparvar

发明人： Frankie F. Roohparvar

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

摘要： A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operation the programs reinforcing data that adjusts the threshold level of the cell to the appropriate level for the desired data.

摘要翻译： 多级单元存储器阵列具有可以被编程为单级单元的区域。 要编程的单元最初被编程为期望数据到单元的最低有效位或最高有效位。 第二编程操作是将所述单元的阈值水平调整到期望数据的适当水平的程序加强数据。

公开(公告)号：US20080158951A1

公开(公告)日：2008-07-03

申请号：US11646658

申请日：2006-12-28

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3431 ,  G11C2211/5648

摘要： The present disclosure includes methods, devices, modules, and systems for programming multilevel non-volatile memory cells, each cell having a number of lower pages and an upper page. One method includes programming a first lower page, programming a second lower page, programming a third lower page, programming an upper page, and reprogramming the upper page of a cell.

摘要翻译： 本公开包括用于编程多级非易失性存储器单元的方法，设备，模块和系统，每个单元具有多个较低页面和上部页面。 一种方法包括编程第一下页，编程第二下页，编程第三下页，编程上页，以及重新编程单元的上页。

公开(公告)号：US07301810B2

公开(公告)日：2007-11-27

申请号：US11616736

申请日：2006-12-27

申请人： Jian Chen

发明人： Jian Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C11/5642 ,  G11C16/3422 ,  G11C2211/5634 ,  G11C2211/5648

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.