Abstract:
According to some embodiments, a device includes a phase generator to generate m control signals, each of the m control signals associated with a respective signal period, and at least m filters, each of the at least m filters comprising m-n taps, each of the m-n taps to receive one of the m control signals, to acquire a signal sample according to a signal period associated with the received control signal, and to modulate the signal sample according to a weighting coefficient associated with the tap. The device further includes m evaluation circuits, each evaluation circuit associated with a respective one of the at least m filters and to output a sum of signal samples modulated by the taps of the associated filter in response to one of the m control signals associated with a signal period other than the signal periods according to which the signal samples were acquired.
Abstract:
A CCD filter according to the present invention can provide good comb-shaped characteristics with no adjustments, and can be produced at low cost. The input section 15 of a first CCD 11 is constructed so that it can linearly reduce transferred charges when an input voltage increases. The input section 17 of a second CCD 12 is constructed so that it can linearly increase transferred charges when the input voltage increases. The transferred charges of the first and second CCDs 11 and 12 are added to each other by means of charge adder section 13, and the addition result is output from an output section 14.
Abstract:
A transversal filter comprises an acoustic charge transport device comprising an input contact for introducing a signal into a buried channel through which the signal is transported by a high frequency acoustic wave and a plurality of non-destructive sense electrodes overlying the channel for successively sampling the signal. A memory device is provided for storing a plurality of tap weight signals, with each tap weight signal for being associated with one of the electrodes. A multiplier system is operably connected with each of the electrodes and with the storage device for generating the product of the signal sampled at each electrode and the associated tap weight signal. A summer is operably associated with the multiplier for summing the products and thereby generating an output signal.
Abstract:
The signal processing apparatus includes a plurality of multiplying or charge splitting stages connected in series. A plurality of pairs of control words are provided, one word of each pair being the complement of the other word of the pair. Each pair of words is associated with a respective multiplying stage and represents the multiplying coefficient of a respective multiplying stage. Means are provided for forming a plurality of quantities of charge, each representing a respective sample of an analog signal. Each of the quantities of charge is introduced in sequence into each of the multiplying stages in which it is processed and then passed on to the next multiplying stage. The process operation in each of the multiplying stages includes dividing the quantity of charge in a series of splitting operations under the control of the pair of words associated with the stage into two parts. All of the first parts of each of the quantities of charge in each of the stages is summed. All of the second part of each of the quantities of charge in each of the stages is summed. A signal is derived representing the difference of the two sums of charge. The two parts of each quantity of charge are combined and passed to the next multiplying stage.
Abstract:
A CCD comb filter is provided employing a basic block having a first, a second and a third delay line wherein particular mixing of the signals from the delay lines results in three outputs having a desired ratio. This basic block is utilized to construct a contour compensation circuit, a drop-out compensation circuit and a 3H delay line. The basic block is versatile and can be utilized for constructing other devices also.
Abstract:
Room acoustics simulation is achieved by digitally defining delay and weighting parameters and generating sampled analog signal responses. In the early portion of a response term an accurate impulse response is provided and subsequently high echo density is simulated using sampled analog signal Schroeder sections. A sampled data analog signal device is used which employs charge transfer devices as programmable delay media, multiplying digital to analog converters to generate weighting of the analog signal and a general purpose microprocessor as a parameter calculator. The early impulse response characteristic is accomplished by providing a time domain finite impulse response (FIR) section in a transversal filter arrangement which directly feeds to an ultimate output and to parallel comb filter sections which in turn input to at least one all pass section of the so-called Schroeder configuration. The charge transfer devices are employed as programmable delays to propagate the analog signals. All weighting coefficient products are generated by multiplying digital-to-analog converters.
Abstract:
A filter utilizing charge transfer devices for providing recursive transfer functions with a transmission zero at d.c. or zero frequency is described. The filter includes a circular charge transfer shift register having an even number N of stages, greater than two, and first, second, third and fourth linear charge transfer shift registers. All five shift registers are clocked at the same frequency. A first input sequence of packets of charge representing positive weight components of a signal, and a second sequence of packets of charge representing negative weight components of the signal are provided. Means are provided for dividing each of the packets of charge of the first input sequence into a first part and a second part and for applying each of the first parts of the packets of the first input sequence to the input stage of the first shift register and for applying each of the second parts of the packets of the first input sequence to the input stage of the second shift register. The charge packet in the first charge storage cell in the K.sup.th stage of the first shift register is combined with the charge packet in the first charge storage cell of the N.sup.th stage of the circular shift register. The combined packet of charge is divided into two portions, a first portion being stored in the first charge storage cell of the K.sup.th stage of the first shift register from which it is clocked out and sensed and a second portion being stored in the first charge storage cell of the N.sup.th stage of the circular shift register. The charge packet in the first charge storage cell of the L.sup.th stage of the second shift register is combined with the charge packet in the M.sup.th stage of the circular shift register, where M is an integer less than N/2 and L=K+M.Means are provided for dividing each of the packets of charge of the second input sequence into a first part and a second part and for applying each of the first parts of the packets of the second input sequence to the input stage of the third shift register and for applying each of the second parts of the packets of the second input sequence to the input stage of the fourth shift register. The charge packet in the first charge storage cell in the K.sup.th stage of the third shift register is combined with the charge packet in the first charge storage cell of the (N/2).sup.th stage of the circular shift register. The combined packet of charge is divided into two portions, a first portion being stored in the first charge storage cell of the K.sup.th stage of the third shift register from which it is clocked out and sensed and a second portion being stored in the first charge storage cell of the (N/2).sup.th stage of the circular shift register. The charge packet in the first charge storage cell of the L.sup.th stage of the fourth shift register is combined with the charge packet in the (N/2+M).sup.th stage of the circular shift register.A first output sequence of packets of charge representing the positive components of an output signal is obtained at the output of the first shift register. A second output sequence of packets of charge representing the negative components of the output signal is obtained at the output of the second shift register. The output signal is obtained by differentially summing corresponding charge packets in the first and second output sequences.
Abstract:
In a filter in which, in order to obtain the desired filter characteristic, a weighted sum of different signals is formed, it is proposed in accordance with the invention that for the formation of said sum means are employed which are constituted by capacitor circuits, which during a first time interval are each charged by said signals, and by a connection circuit for the formation, during a second time interval, of the equivalent of a single capacitor across whose plates the weighted-sum signal appears.The invention is used for the filtration of sampled analog signals.
Abstract:
Disclosed is a charge transfer device, like a transversal filter, having means for detecting if an amount of signal charge transferred from one stage to another falls within a dynamic range of the device. A charge transfer channel is so formed as to have first and second branched output ports. A signal charge transferred to the first output port is detected as an output signal supplied to a utilization circuit while an output voltage caused by a signal charge transferred to the second output port is compared with first and second reference voltages which correspond to first and second amounts of signal charges substantially determining upper and lower limits of the dynamic range of the device, whereby it is detected if the amount of the signal charge transferred is within the dynamic range or not. As a result of the detection when the signal charge amount is outside the dynamic range, the supply of the output signal to the utilization circuit is interrupted.
Abstract:
The process more particularly comprises introducing beneath the final storage capacitor C.sub.6 a quantity of charges equal to that located there during the processing of the preceding sample of the input signal, prior to the beginning of charge transfer from said capacitors to the means which convert the charges into a voltage, and distributing the charges between said capacitor and the preceding capacitor as a function of the capacitance values. The switched capacitor filter more particularly comprises, when it is looped, a circuit R permitting the application to the looping capacitor C.sub.4 of a voltage V.sub.g +.DELTA.V.sub.s, while the foils of the other storage capacitors of the filter are connected to the voltage V.sub.g.