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    3-dimensional NOR strings with segmented shared source regions
    53.
    发明授权
    3-dimensional NOR strings with segmented shared source regions 有权

    公开(公告)号：US10950616B2

    公开(公告)日：2021-03-16

    申请号：US16792808

    申请日：2020-02-17

    申请人： Sunrise Memory Corporation

    发明人： Eli Harari ,  Raul Adrian Cernea

    IPC分类号： H01L27/11 ,  G11C16/04 ,  H01L27/11578 ,  G11C7/18 ,  H03K19/20 ,  H03K19/1776 ,  G11C16/08 ,  G11C16/24 ,  H01L29/786

    摘要： A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

    BINARY-TO-TERNARY CONVERTER USING A COMPLEMENTARY RESISTIVE SWITCH
    55.
    发明申请
    BINARY-TO-TERNARY CONVERTER USING A COMPLEMENTARY RESISTIVE SWITCH 有权

    公开(公告)号：US20210020238A1

    公开(公告)日：2021-01-21

    申请号：US16980211

    申请日：2018-03-23

    申请人： NEC Corporation

    发明人： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Makoto MIYAMURA ,  Ryusuke NEBASHI ,  Ayuka TADA

    IPC分类号： G11C13/00 ,  H03M5/02 ,  H03K19/1776

    摘要： A reconfigurable circuit includes: a complementary resistive switch including a first resistive switch, a second resistive switch and a selection transistor, wherein a first terminal of the first resistive switch is connected to a first terminal of the second resistive switch and connected to a first terminal of the selection transistor; a first current source having a first terminal connected to a second terminal of the first resistive switch and a second terminal connected to a ground voltage line; a second current source having a first terminal connected to a second terminal of the second resistive switch and a second terminal connected to the ground voltage line; and a resistor having a first terminal connected to a second terminal of the selection transistor and a second terminal connected to a power voltage line.

    Bonding structure of dies with dangling bonds
    56.
    发明授权
    Bonding structure of dies with dangling bonds 有权

    公开(公告)号：US10861808B2

    公开(公告)日：2020-12-08

    申请号：US16371863

    申请日：2019-04-01

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hsien-Wei Chen ,  Ming-Fa Chen ,  Chih-Chia Hu

    IPC分类号： H01L23/498 ,  H01L23/00 ,  H03K19/1776 ,  H01L23/495

    摘要： A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.

    Electronic Control Device and Error Detection Method of Configuration Memory
    57.
    发明申请
    Electronic Control Device and Error Detection Method of Configuration Memory 审中-公开

    公开(公告)号：US20200379831A1

    公开(公告)日：2020-12-03

    申请号：US16970855

    申请日：2018-11-20

    申请人： Hitachi Automotive Systems, Ltd.

    发明人： Kenichi SHIMBO ,  Tadanobu TOBA ,  Taisuke UETA ,  Hideyuki SAKAMOTO

    IPC分类号： G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  H03K19/1776

    摘要： An electronic control device includes a rewritable configuration memory composed of a plurality of frames in which logic circuit information is stored, a reconfiguration control unit configured to rewrite the logic circuit information of the frames, a logic unit configured to form a logic circuit based on the logic circuit information stored in the frames, and a configuration memory diagnosis unit configured to read the logical circuit information stored in the frames of the configuration memory and to perform error detection which is detection of an error in the stored logic circuit information, in which when the frames are rewritten by the reconfiguration control unit, the configuration memory diagnosis unit performs the error detection of ones of the frames that are rewritten prior to ones of the frames that are not rewritten.

    Data interpolation
    59.
    发明授权
    Data interpolation 有权

    公开(公告)号：US10817493B2

    公开(公告)日：2020-10-27

    申请号：US15644021

    申请日：2017-07-07

    申请人： Raytheon Company

    发明人： James R. Sackett

    IPC分类号： G06F16/00 ,  G06F12/00 ,  H03K19/10 ,  G06F16/22 ,  H03K19/17704 ,  H03K19/17728 ,  G06F12/02 ,  H03K19/1776 ,  H01L27/28

    摘要： Generally discussed herein are systems, devices, and methods for data interpolation. A system for data interpolation can include first circuitry to split a set of data into four disjoint subsets including first, second, third, and fourth subsets and load each of the disjoints subsets into respective first, second, third, and fourth memory portions, second circuitry to retrieve, simultaneously, data from each of the first, second, third, and fourth memory portions, and interpolation circuitry to perform, based on the retrieved data, data interpolation.

    METHOD FOR PROGRAMMING A FIELD PROGRAMMABLE GATE ARRAY AND NETWORK CONFIGURATION
    60.
    发明申请
    METHOD FOR PROGRAMMING A FIELD PROGRAMMABLE GATE ARRAY AND NETWORK CONFIGURATION 审中-公开

    公开(公告)号：US20200321965A1

    公开(公告)日：2020-10-08

    申请号：US16957428

    申请日：2017-12-28

    申请人： Unify Patente GmbH & Co. KG

    发明人： Marcelo Samsoniuk ,  Paolo Henrique Bernardi ,  Diogo Wachtel Granado

    IPC分类号： H03K19/17764 ,  H03K19/1776 ,  H03K19/17736 ,  H03K19/17704

    摘要： A method for programming a Field Programmable Gate Array (FPGA) via a network, the network being operated according to a predetermined communications protocol, can include: establishing a communication connection between the FPGA and an external master, setting the FPGA into a programming mode, the master providing an FPGA programming image to the FPGA in a sequence of frames so that the frames can be parsed and enabling the FPGA to write only during receiving the payload section of the frames. The FPGA programming image and parsing the sequence of frames can be performed by a permanently programmed or hardwired logic component. A network, FPGA, and a communication system can be configured to utilize embodiments of the method.