公开(公告)号：US20200228132A1

公开(公告)日：2020-07-16

申请号：US16524401

申请日：2019-07-29

Applicant: Realtek Semiconductor Corporation

Inventor： Shih-Hsiung HUANG

IPC: H03M1/38

Abstract: An analog-to-digital converter (ADC) device includes capacitor arrays, a successive approximation register (SAR) circuitry, and a switching circuitry. When a first capacitor array of the capacitor arrays samples an input signal in a first phase, a second capacitor array of the capacitor arrays outputs the input signal sampled in a second phase as a sampled input signal. The SAR circuitry performs an analog-to-digital conversion on a combination of the sampled input signal and a residue signal generated in the second phase according to a conversion clock signal, in order to generate a digital output. The switching circuitry includes a first capacitor that stores the residue signal generated in the second phase. The switching circuitry couples the second capacitor array and the first capacitor to an input terminal of the SAR circuitry, in order to provide the combination of the sampled input signal and the residue signal.

公开(公告)号：US10666283B2

公开(公告)日：2020-05-26

申请号：US16244003

申请日：2019-01-09

Applicant: SOCIONEXT INC.

Inventor： Niklas Linkewitsch ,  Charles Joseph Dedic

IPC: H03M1/38 ,  H03M1/46 ,  H03M1/12

Abstract: The present invention relates to analogue-to-digital converter (ADC) circuitry. In particular, the present invention relates to ADC circuitry configured to use successive approximation to arrive at a multi-bit digital value representative of an analogue input value.

公开(公告)号：US10606294B1

公开(公告)日：2020-03-31

申请号：US16240778

申请日：2019-01-06

Applicant: NOVATEK Microelectronics Corp.

Inventor： Liang-Ting Kuo ,  Mu-Jung Chen ,  Chi-Chun Liao

IPC: G05F1/575 ,  H03M1/38 ,  H03M1/06 ,  H02M1/14

Abstract: A low dropout voltage regulator, coupled to a load circuit receiving a clock signal, includes an amplifier; a power transistor comprising a control terminal, coupled to an output terminal of the amplifier; and a first terminal, coupled to a positive input terminal of the amplifier and the load circuit; and a control circuit, configured to control a current flowing through the power transistor in response to the clock signal.

公开(公告)号：US20200057484A1

公开(公告)日：2020-02-20

申请号：US16103963

申请日：2018-08-16

Applicant: Analog Devices, Inc.

Inventor： Michael C.W. Coln ,  Michael Mueck

IPC: G06F1/32 ,  H03F3/45 ,  H03M1/38 ,  H03M1/12

Abstract: A signal acquisition or conditioning amplifier can be configured and controlled to use correlated doubling sampling (CDS) of a differential input signal, and a storage capacitor in a capacitive or other feedback network, a low power operational transconductance amplifier (OTA) capable of being powered down between CDS samplings, and which can be operated in a manner that provides good performance characteristics while still providing low or efficient power consumption. The amplifier and other signal processing circuitry can allow power to be scaled down, when less signal measurement throughput is needed, and to be scaled up, when more signal measurement throughput is needed. Such flexibility can help make the present approach useful for a wide range of signal acquisition and measurement applications. Precharging via buffer amplifiers can provide improved signal acquisition circuitry effective input impedance.

公开(公告)号：US10541704B2

公开(公告)日：2020-01-21

申请号：US16285537

申请日：2019-02-26

Applicant: MEDIATEK INC.

Inventor： Tzu-Chien Wu

IPC: H03M1/38 ,  H03M1/46 ,  H03M1/16 ,  H03M1/40 ,  H03M1/06 ,  H03M1/80

Abstract: A pipelined analog-to-digital converter (ADC) using a multiplying digital-to-analog converter (MDAC) and two sub-range analog-to-digital converters (sub-range ADCs) is disclosed. The MDAC samples an analog input and performs multiplication on the sampled analog input based on control bits. The first sub-range ADC provides the MDAC with the control bits. The second sub-range ADC is coupled to the MDAC for conversion of a multiplied signal output from the MDAC. The first sub-range ADC samples the analog input to generate the control bits for the MDAC as well as pre-estimated bits for the second sub-range ADC. The second sub-range ADC operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range ADC. A second section of digital bits are provided by the first sub-range ADC. The first and second sections of digital bits represent the analog input.

公开(公告)号：US10523231B1

公开(公告)日：2019-12-31

申请号：US16233642

申请日：2018-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya KrishnaSwamy Nurani ,  Shagun Dusad ,  Visvesvaraya Appala Pentakota

IPC: H03M1/38 ,  H03M1/16 ,  H03M1/12 ,  H03M1/46

Abstract: A pipelined analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue stage coupled to the first ADC stage. The residue stage includes a dynamic integrator configured to provide transconductance, wherein the dynamic integrator includes a boost circuit configured to boost an output impedance of the transconductance.

公开(公告)号：US10469095B2

公开(公告)日：2019-11-05

申请号：US16119117

申请日：2018-08-31

Applicant: NXP B.V.

Inventor： Yu Lin ,  Erwin Janssen ,  Vladislav Dyachenko

IPC: H03M1/38 ,  H03M1/18 ,  G01S13/06 ,  H03M1/10 ,  H03M1/46

Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.

公开(公告)号：US20190268557A1

公开(公告)日：2019-08-29

申请号：US16349016

申请日：2017-11-09

Applicant: NATIONAL UNIVERSITY CORPORATION SHIZUOKA UNIVERSITY

Inventor： Shoji KAWAHITO

IPC: H04N5/378 ,  H03M1/14 ,  H03M1/38 ,  H04N5/376

Abstract: An A/D converter 1 includes a front stage A/D conversion unit (3) including a first A/D conversion unit (6) that receives an analog signal from a CMOS image sensor (100) and generates a first digital value (D1) and a first residual analog signal (VOPF) through a folding integration A/D conversion operation, and a second A/D conversion unit (7) that receives a first residual analog signal (VOPF) from the first A/D conversion unit (6) and generates a second digital value (D2) and a second residual analog signal (VOPC) through a cyclic A/D conversion operation, and a rear stage A/D conversion unit (4) that receives the second residual analog signal (VOPC) from the front stage A/D conversion unit (3) and generates a third digital value (D3) through an acyclic A/D conversion operation.

公开(公告)号：US10355707B2

公开(公告)日：2019-07-16

申请号：US15901294

申请日：2018-02-21

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris

IPC: H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03M1/10 ,  H03M1/38 ,  H03M1/00 ,  H03M1/18 ,  H02M3/156 ,  H03K5/00 ,  H03M1/50

Abstract: Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

公开(公告)号：US10312868B2

公开(公告)日：2019-06-04

申请号：US15957927

申请日：2018-04-20

Applicant: Aura Semiconductor Pvt. Ltd

Inventor： Arnold J D'Souza ,  Shyam Somayajula

IPC: H03F3/45 ,  H03F1/32 ,  H03F3/21 ,  H03F1/02 ,  H03M1/38

Abstract: A fully differential amplifier includes a first feedback resistance, a second feedback resistance, a first input resistance and a second input resistance. A first ratio of the first feedback resistance to the first input resistance is equalized with that of a reference ratio of a pair of reference resistances. Similarly a second ratio of the second feedback resistance to the second input resistance is also equalized with that of the reference ratio. Such equalization operations may be performed during a calibration phase prior to normal operation of the fully differential amplifier. Accordingly, when a common mode voltage present on each of the first output terminal and the second output terminal varies during normal operation, contribution of an erroneous differential signal component across the pair of differential output terminals is prevented.