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    APPARATUS AND METHOD FOR CONTROLLING OPERATION OF MACHINE
    632.
    发明申请
    APPARATUS AND METHOD FOR CONTROLLING OPERATION OF MACHINE 审中-公开

    公开(公告)号：US20190276930A1

    公开(公告)日：2019-09-12

    申请号：US15950152

    申请日：2018-04-10

    Applicant: United Microelectronics Corp.

    Inventor： Neng-Hsing Shen ,  Chien-Wen Yang ,  Chun-Man Li ,  Ji-Fu Kung ,  Ching-Pei Lin

    IPC: C23C14/54 ,  C23C14/48 ,  H01L21/66 ,  G05B15/02 ,  G06K9/00

    Abstract: An apparatus for controlling an operation of a machine includes an optical recognition system, a control unit, and a remote control interface. The optical recognition system is configured to monitor and obtain actual operation information displayed on a panel of a processing machine in accordance with an operation time. The control unit is configured to receive the actual operation information and check the actual operation information with expected operation information. The expected operation information is obtained based on an operation model which is already built up corresponding to a current fabrication process. Deviation information between the actual operation information and the expected operation information is determined and converted into a parameter set. The remote control interface receives the parameter set and converts the parameter set into a control signal set to control the operation of the processing machine.

    Semiconductor structure and manufacturing method thereof
    633.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US10411110B1

    公开(公告)日：2019-09-10

    申请号：US16053657

    申请日：2018-08-02

    Applicant: United Microelectronics Corp.

    Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang

    IPC: H01L29/732 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

    Abstract: A semiconductor structure including a substrate, a BJT, a first interconnect structure and a second interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The BJT is located at the first side. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. The first interconnect structure is located at the first side and electrically connected to the base. The second interconnect structure is located at the second side and electrically connected to the collector. The first interconnect structure further extends to the second side. The first interconnect structure and the second interconnect structure are respectively electrically connected to an external circuit at the second side. The semiconductor structure can have better overall performance.

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    634.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190273117A1

    公开(公告)日：2019-09-05

    申请号：US16297698

    申请日：2019-03-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Wen Hung ,  Yu-Ping Wang

    IPC: H01L27/22 ,  G11C11/16 ,  H01F41/34 ,  H01F10/32 ,  H01L43/12 ,  H01L23/522 ,  H01L43/08 ,  H01L23/528 ,  H01L43/02

    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, first plug, a magnetoresistive random access memory (MRAM) structure, a spacer layer, a seal layer and a first conductive pattern. The substrate has a first region and a second region, and the first plug is disposed on a dielectric layer disposed on the substrate, within the first region. The MRAM structure is disposed in the dielectric layer and electrically connected to the first plug. The spacer layer is disposed both within the first region and the second region, to cover the MRAM structure. The seal layer is disposed on the MRAM structure and the first plug, only within the first region. The first conductive pattern penetrates through the seal layer to electrically connect the MRAM structure.

    SEMICONDUCTOR DEVICE
    636.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190267373A1

    公开(公告)日：2019-08-29

    申请号：US16407188

    申请日：2019-05-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

    Semiconductor device
    637.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10396157B1

    公开(公告)日：2019-08-27

    申请号：US15913533

    申请日：2018-03-06

    Applicant: United Microelectronics Corp.

    Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

    IPC: H01L27/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

    Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

    Layout pattern for SRAM and manufacturing methods thereof
    639.
    发明授权
    Layout pattern for SRAM and manufacturing methods thereof 有权

    公开(公告)号：US10396064B2

    公开(公告)日：2019-08-27

    申请号：US16171339

    申请日：2018-10-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

    IPC: H01L27/02 ,  G03F1/36 ,  G06F17/50 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11

    Abstract: The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit.

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