公开(公告)号：US20060010262A1

公开(公告)日：2006-01-12

申请号：US11154281

申请日：2005-06-16

Applicant: Daniele Fronte ,  Jean Nicolai ,  Albert Martinez

Inventor： Daniele Fronte ,  Jean Nicolai ,  Albert Martinez

IPC: G06F13/28 ,  G06F12/08

CPC classification number: G06F13/28

Abstract: A method is provided for processing a virtual address for a program requesting a DMA transfer. The program is designed to be run in user mode on a system on a chip that includes a central processing unit, a memory management unit, and a DMA controller. The virtual address is a source virtual address or a destination virtual address and has a size of N bits. According to the method, the virtual address is divided into at least two fields of bits. For each of the fields, there is created an N-bit address word comprising a prefix having a given value associated with the field and having more than 1 bit, and the field. The DMA controller is programmed using multiple store instructions that include one store instruction relating to each of the address words created.

Abstract translation: 提供了一种用于处理请求DMA传输的程序的虚拟地址的方法。 该程序被设计为在包括中央处理单元，存储器管理单元和DMA控制器的芯片上的系统上以用户模式运行。 虚拟地址是源虚拟地址或目标虚拟地址，并且具有N位的大小。 根据该方法，虚拟地址被分成至少两个比特字段。 对于每个字段，创建了包括具有与该字段相关联并具有多于1位的给定值的前缀的N位地址字和该字段。 使用多个存储指令对DMA控制器进行编程，其中包括与创建的每个地址字相关的一个存储指令。

公开(公告)号：US20050268163A1

公开(公告)日：2005-12-01

申请号：US11111018

申请日：2005-04-21

Applicant: Frederic Bancel ,  Nicolas Berard

Inventor： Frederic Bancel ,  Nicolas Berard

IPC: G06F11/00 ,  G06F21/00

CPC classification number: G06F21/71 ,  G06F21/52

Abstract: A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. Current cumulative signatures are produced using deterministic address, control or data logic signals involved in the execution of the sequence and taken off at various points of the integrated circuit. A final cumulative signature is compared with an expected signature and an error signal is produced if the two signatures are not identical. Particularly useful to secure integrated circuits for smart cards.

Abstract translation: 一种用于监视集成电路中的指令代码序列的执行的方法，该集成电路包括用于执行这种指令代码的中央处理单元。 使用确定性地址，控制或数据逻辑信号产生当前累积签名，该信号涉及序列的执行并在集成电路的各个点被取消。 将最终累积签名与预期签名进行比较，如果两个签名不相同，则产生错误信号。 特别适用于安全智能卡的集成电路。

公开(公告)号：US06971020B1

公开(公告)日：2005-11-29

申请号：US09506158

申请日：2000-02-17

Applicant: Pierre-Yvan Liardet ,  Fabrice Romain ,  Bernard Plessier ,  Brigitte Hennebois

Inventor： Pierre-Yvan Liardet ,  Fabrice Romain ,  Bernard Plessier ,  Brigitte Hennebois

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30 ,  G06F17/00

CPC classification number: H04L9/06 ,  H04L9/0894 ,  H04L2209/12

Abstract: A circuit and a method are provided for securing a coprocessor dedicated to cryptography. The disclosed circuit includes a scrambling register and an accessory input register to convey scrambling information in the form of electrical signals that disturb the visibility of certain electrical signals associated with confidential information such as digital keys.

Abstract translation: 提供了一种用于保护专用于密码学的协处理器的电路和方法。 所公开的电路包括加扰寄存器和附件输入寄存器，以电信号的形式传送加扰信息，该电信号干扰与机密信息（例如数字密钥）相关联的某些电信号的可视性。

公开(公告)号：US20050251708A1

公开(公告)日：2005-11-10

申请号：US11111046

申请日：2005-04-21

Applicant: Frederic Bancel ,  Nicolas Berard

Inventor： Frederic Bancel ,  Nicolas Berard

IPC: G06F11/00 ,  G06F21/00

CPC classification number: G06F21/71 ,  G06F21/52

Abstract: A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. In one embodiment, the method comprises producing current cumulative signatures during the execution of a sequence, until a final cumulative signature is obtained, producing an error signal having a value active by default while the current cumulative signature is different to an expected signature, measuring a predetermined time interval that is substantially longer than the presumed duration of execution of the sequence, masking the error signal during the measurement of the time interval, and lifting the masking of the error signal when the time interval expires.

Abstract translation: 一种用于监视集成电路中的指令代码序列的执行的方法，该集成电路包括用于执行这种指令代码的中央处理单元。 在一个实施例中，该方法包括在执行序列期间产生当前的累积签名，直到获得最终的累积签名，产生一个错误信号，该错误信号在当前累积签名与预期签名不同的情况下默认为有效值， 比预定的序列执行持续时间长的预定时间间隔，在时间间隔的测量期间屏蔽误差信号，并且当时间间隔到期时提升误差信号的掩蔽。

公开(公告)号：US20050249286A1

公开(公告)日：2005-11-10

申请号：US11117063

申请日：2005-04-28

Applicant: Marina Nicolas

Inventor： Marina Nicolas

IPC: H04N5/14 ,  H04N7/26 ,  H04N7/46 ,  H04N7/12

CPC classification number: H04N5/145 ,  H04N19/51 ,  H04N19/577

Abstract: A motion estimation method and device are provided for processing images to be inserted, between a preceding original image and a following original image, in a sequence of images. Each of the images is divided into several pixel blocks. A motion vector is associated with each block of a processed image. For a current block of an image currently being processed, motion vectors associated with blocks of the image currently being processed and/or of an already processed image are selected. For each motion vector selected, an updating vector is determined. Candidate vectors are generated from the selected motion vectors and the updating vectors. A vector is elected from among the candidate vectors. Information associating the elected motion vector with the current block is stored in memory. The updating vector is determined on the basis of a calculated confidence value stored in memory for each associated motion vector.

Abstract translation: 提供了一种运动估计方法和装置，用于在一系列图像中处理在前一原始图像和下一个原始图像之间插入的图像。 每个图像被分成几个像素块。 运动矢量与处理后的图像的每个块相关联。 对于当前正在处理的图像的当前块，选择与当前正在处理的图像的块相关联的运动矢量和/或已经处理的图像的运动矢量。 对于选择的每个运动矢量，确定更新向量。 从选定的运动矢量和更新向量生成候选向量。 从候选向量中选出一个向量。 将所选运动矢量与当前块相关联的信息存储在存储器中。 基于对于每个相关联的运动矢量存储在存储器中的计算的置信度来确定更新向量。

公开(公告)号：US20050246600A1

公开(公告)日：2005-11-03

申请号：US11070850

申请日：2005-03-02

Applicant: Pierre Pistoulet

Inventor： Pierre Pistoulet

IPC: G01R31/28 ,  G01R31/317 ,  G06F7/02 ,  H03M13/00

CPC classification number: G01R31/31719

Abstract: A logic circuit comprises a logic module comprising a functional logic block supplying a functional result, and a functional flip-flop receiving the functional result and supplying a synchronous result. A module for checking the functional logic block comprises a checking logic block executing the same logic function as the functional logic block and supplying a checking result, checking synchronous flip-flops for applying data present at the input of the functional logic block to the input of the checking logic block, and means for comparing the functional result and the checking result and for supplying a first error signal.

Abstract translation: 逻辑电路包括逻辑模块，该逻辑模块包括提供功能结果的功能逻辑块，以及接收功能结果并提供同步结果的功能触发器。 用于检查功能逻辑块的模块包括执行与功能逻辑块相同的逻辑功能并提供检查结果的检查逻辑块，检查同步触发器以将存在于功能逻辑块的输入端的数据应用于 检查逻辑块，以及用于比较功能结果和检查结果并用于提供第一误差信号的装置。

公开(公告)号：US06960936B2

公开(公告)日：2005-11-01

申请号：US10770836

申请日：2004-02-03

Applicant: Joël Cambonie

Inventor： Joël Cambonie

IPC: G06F15/78 ,  H03K19/177 ,  G06F7/38

CPC classification number: H03K19/17736 ,  G06F15/7867 ,  H03K19/17732 ,  H03K19/1774 ,  Y02D10/12 ,  Y02D10/13

Abstract: The configurable electronic device comprises a configurable electronic device includes at least one configurable basic assembly. The basic assembly includes a programmable circuit having a plurality of programmable elements, and a first configurable interconnection network for mutually connecting the programmable circuits. A plurality of configurable arithmetic cells are mutually connected by a second configurable interconnection network. A third configurable interconnection network links the programmable circuit and the configurable arithmetic cells. A control bus is between the programmable circuit and the configurable arithmetic cells, and also extends within the configurable arithmetic cells.

Abstract translation: 可配置电子设备包括可配置电子设备，其包括至少一个可配置的基本组件。 基本组件包括具有多个可编程元件的可编程电路和用于相互连接可编程电路的第一可配置互连网络。 多个可配置的算术单元通过第二可配置互连网络相互连接。 第三可配置互连网络链接可编程电路和可配置的算术单元。 控制总线在可编程电路和可配置的算术单元之间，并且还可在可配置的算术单元内延伸。

公开(公告)号：US20050232021A1

公开(公告)日：2005-10-20

申请号：US11106048

申请日：2005-04-14

Applicant: Mathieu Lisart

Inventor： Mathieu Lisart

IPC: G11C7/24 ,  G11C16/22 ,  G11C16/26 ,  G11C17/00

CPC classification number: G11C16/26 ,  G11C16/22

Abstract: The present invention relates to a non-volatile memory comprising a memory array comprising functional memory cells and non-functional memory cells linked to at least one non-functional word line. A word line address decoder comprises a special decoding section linked to the non-functional word line, for selecting the non-functional word line when a functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells, and distort the reading of the functional memory cells. Application particularly to integrated circuits for smart cards.

Abstract translation: 非易失性存储器技术领域本发明涉及一种非易失性存储器，其包括存储器阵列，该存储器阵列包括与至少一个非功能字线连接的功能存储器单元和非功能存储器单元。 字线地址解码器包括链接到非功能字线的特殊解码部分，用于当功能字线被读取选择时选择非功能字线，使得与功能性字符串同时选择非功能性存储器单元 存储单元，并扭曲功能存储单元的读数。 特别适用于智能卡集成电路。

公开(公告)号：US20050212084A1

公开(公告)日：2005-09-29

申请号：US11009695

申请日：2004-12-10

Applicant: Sebastien Grange

Inventor： Sebastien Grange

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/552 ,  H05K1/02 ,  H01L29/00

CPC classification number: H01L23/5227 ,  H01L23/49816 ,  H01L23/552 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/3025

Abstract: A chip circuit comprising a chip which comprises a semiconductor substrate and substantially plane components formed on the said substrate, among which there are an emitting component capable of emitting electromagnetic radiation and an inductor sensitive to the incident electromagnetic radiation. At least one shield, external to the chip, is placed opposite the inductor at a distance of less than 500 microns. The shield thus makes it possible to shield the sensitive inductor from the emitting component, while maintaining the quality factor of the inductor.

Abstract translation: 一种芯片电路，包括芯片，其包括半导体衬底和形成在所述衬底上的基本上平面的部件，其中存在能够发射电磁辐射的发射部件和对入射的电磁辐射敏感的电感器。 在芯片外部的至少一个屏蔽件以小于500微米的距离放置在电感器的对面。 因此，屏蔽因此可以在保持感应器的品质因数的同时屏蔽敏感电感器与发光元件。

公开(公告)号：US20050206431A1

公开(公告)日：2005-09-22

申请号：US10915248

申请日：2004-08-09

Applicant: Richard Fournel

Inventor： Richard Fournel

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0013 ,  H03K19/018521

Abstract: An interface circuit for transforming a first signal varying between a low voltage and a high voltage into a second signal varying between a lower voltage and a higher voltage, the lower voltage being smaller than the low voltage and/or the higher voltage being greater than the high voltage, comprising: an inverter circuit receiving the first signal and being connected for its supply between said higher voltage and said lower voltage, one at least of these connections being performed via at least one diode, a conversion element supplied between said higher and lower voltages, and receiving the output of the inverter circuit and providing the second signal, a storage element capable of maintaining the output of the inverter circuit at said higher or lower voltage when the first signal is respectively equal to the low or high voltage.

Abstract translation: 一种用于将在低电压和高电压之间变化的第一信号变换成在较低电压和较高电压之间变化的第二信号的接口电路，所述较低电压小于所述低电压和/或所述较高电压大于 高电压，包括：反相器电路，接收所述第一信号，并且在所述较高电压和所述较低电压之间连接供电，所述至少一个连接通过至少一个二极管执行，所述转换元件在所述较高和较低电压之间提供 电压，并且接收逆变器电路的输出并提供第二信号，当第一信号分别等于低电压或高电压时，能够将逆变器电路的输出保持在所述较高或较低电压的存储元件。