公开(公告)号：US20130294142A1

公开(公告)日：2013-11-07

申请号：US13887167

申请日：2013-05-03

Applicant: STMICROELECTRONICS SA

Inventor： Philippe Candelier ,  Joel Damiens ,  Elise Leroux

IPC: G11C17/16

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L27/101 ,  H01L27/11206

Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

公开(公告)号：US20130292824A1

公开(公告)日：2013-11-07

申请号：US13873103

申请日：2013-04-29

Applicant: STMICROELECTRONICS SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L23/28 ,  H01L23/538 ,  H01L21/768

CPC classification number: H01L23/28 ,  H01L21/486 ,  H01L21/76877 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5384 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

Abstract: A chip provided with through vias wherein the vias are formed of an opening with insulated walls coated with a conductive material and filled with an easily deformable insulating material, elements of connection to another chip being arranged in front of the easily deformable insulating material.

Abstract translation: 具有通孔的芯片，其中通孔由具有绝缘壁的开口形成，绝缘壁涂覆有导电材料，并且填充有易变形的绝缘材料，与另一芯片的连接元件布置在容易变形的绝缘材料的前面。

公开(公告)号：US20130283322A1

公开(公告)日：2013-10-24

申请号：US13921337

申请日：2013-06-19

Applicant: STMICROELECTRONICS SA

Inventor： PIERRE BUSSON ,  BERNARD LOUIS-GAVET ,  PIERRE-OLIVIER JOUFFRE

IPC: H04N21/61

CPC classification number: H04N21/6143 ,  H04L27/06 ,  H04N7/20

Abstract: The component, fully integrated onto a monolithic substrate, includes a tuner, a demodulator, and a channel decoder. The overall filtering is carried out in two parts, a baseband analog filtering and a digital Nyquist filtering removing the information of adjacent channels. It outputs a stream of MPEG data.

Abstract translation: 完全集成到单片基板上的部件包括调谐器，解调器和通道解码器。 整体滤波分为两部分：基带模拟滤波和数字奈奎斯特滤波，去除相邻信道的信息。 它输出一个MPEG数据流。

公开(公告)号：US20130214976A1

公开(公告)日：2013-08-22

申请号：US13768707

申请日：2013-02-15

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Thierry Michel ,  Bruno Paille

IPC: G01S5/14

CPC classification number: G01S5/14 ,  G01S5/0221 ,  G01S5/06 ,  H04B1/707

Abstract: A method for localizing an object, including the acts of: transmission of a first signal by a first transmitter assigned to the object and of a second signal by at least one second transmitter; reception of the first and of the second signal by at least three receivers; in each receiver and for the first and the second signal: a) generation of a first and of a second reference signal; b) correlation between the first signal and the first reference signal and between the second signal and the second reference signal; c) interpolation of samples resulting from the correlation; d) deduction of the propagation time of the first and of the second signal; e) calculation of the difference between the propagation times of the first and of the second signal; and, by triangulation, deduction of the position of the object.

Abstract translation: 一种用于定位对象的方法，包括以下动作：由分配给对象的第一发射机传输第一信号，以及由至少一个第二发射机传输第二信号; 由至少三个接收器接收第一和第二信号; 在每个接收机中以及对于第一和第二信号：a）产生第一和第二参考信号; b）第一信号和第一参考信号之间以及第二信号和第二参考信号之间的相关; c）由相关产生的样本的插值; d）扣除第一和第二信号的传播时间; e）计算第一和第二信号的传播时间之差; 并通过三角测量来扣除物体的位置。

公开(公告)号：US20130157562A1

公开(公告)日：2013-06-20

申请号：US13714151

申请日：2012-12-13

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pascal Urard ,  Christophe Regnier ,  Daniel Gloria ,  Olivier Hinsinger ,  Philippe Cavenel ,  Lionel Balme

IPC: H04B7/24

CPC classification number: H04B5/0031 ,  G06F1/1694 ,  G06F1/1698 ,  G06F3/017 ,  G06F21/35 ,  H04B7/24 ,  H04L63/0869 ,  H04L63/18 ,  H04W4/008 ,  H04W4/80 ,  H04W12/06 ,  H04W12/08

Abstract: A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit.

Abstract translation: 无线单元包括第一运动敏感设备; 用于与另一无线单元无线通信的通信电路; 以及处理装置，被配置为将从所述第一运动敏感装置接收的至少一个第一运动矢量与从所述另一无线单元的第二运动敏感装置接收的至少一个第二运动矢量进行比较。

公开(公告)号：US20130155303A1

公开(公告)日：2013-06-20

申请号：US13711037

申请日：2012-12-11

Applicant: STMicroelectronics SA

Inventor： Frederic BARBIER

IPC: H04N5/335

CPC classification number: H04N5/335 ,  H01L27/14641 ,  H04N3/155 ,  H04N5/347 ,  H04N5/3532 ,  H04N5/3559 ,  H04N5/374 ,  H04N5/37452

Abstract: A method may include a cycle of reading a current pixel including connecting the capacitive node of the pixel to a capacitive node of a previous pixel already read, connecting the capacitive node of the current pixel and the capacitive node of a previous pixel to an output line, reading a first voltage of the capacitive node of the pixel through the output line, transferring charges from the accumulation node to the capacitive node of the pixel, reading a second voltage of the capacitive node of the pixel through the output line, and disconnecting the capacitive node from the capacitive node of a previous pixel, and a cycle of reading a next pixel. This cycle may include accumulating charges in the accumulation node of the next pixel while the capacitive node of the current pixel is connected to a capacitive node of a previous pixel.

Abstract translation: 方法可以包括读取当前像素的循环，包括将像素的电容性节点连接到已经读取的先前像素的电容性节点，将当前像素的电容性节点和先前像素的电容性节点连接到输出线 通过输出线读取像素的电容性节点的第一电压，将电荷从累积节点传送到像素的电容性节点，通过输出线读取像素的电容性节点的第二电压，并且断开 来自先前像素的电容性节点的电容性节点以及读取下一个像素的周期。 该周期可以包括在下一个像素的累积节点中积累电荷，而当前像素的电容节点连接到先前像素的电容节点。

公开(公告)号：US20130142227A1

公开(公告)日：2013-06-06

申请号：US13651883

申请日：2012-10-15

Applicant: STMicroelectronics SA ,  STMicroelectronics (R&D) Ltd ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Andrew FERRIS ,  Ignazio Antonino URZI ,  Pascal TEISSIER

IPC: H04B1/38

CPC classification number: G06F13/423

Abstract: A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications.

Abstract translation: 电路包括第一n比特通信块和第二m比特通信块。 控制器被配置为控制第一和第二通信块的操作模式。 在第一模式中，第一和第二通信块用作n + m位通信的单个通信块。 在第二模式中，第一和第二通信块作为用于n位通信和m位通信的基本上独立的通信块来操作。

公开(公告)号：US20130120087A1

公开(公告)日：2013-05-16

申请号：US13736913

申请日：2013-01-08

Applicant: STMICROELECTRONICS SA

Inventor： Sébastien PRUVOST ,  Frédéric GIANESSELLO

IPC: H01P3/00

CPC classification number: H01P3/003 ,  H01P3/006 ,  H01P3/082

Abstract: An embodiment relates to a coplanar waveguide electronic device comprising a substrate whereon is mounted a signal ribbon and at least a ground plane. The signal ribbon comprises a plurality of signal lines of a same level of metallization electrically connected together, and the ground plane is made of an electrically conducting material and comprises a plurality of holes.

公开(公告)号：US20130120049A1

公开(公告)日：2013-05-16

申请号：US13666727

申请日：2012-11-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H03K17/72

CPC classification number: H03K17/063 ,  H01L27/0262

Abstract: A power switch includes first and second MOS transistors in series between first and second nodes. Both the first and second transistors have a gate coupled to its substrate. First and second resistive elements are coupled between the gate of the first transistor and the first node, and between the gate of the second transistor and the second node, respectively. A triac is coupled between the first and second nodes. The gate of the triac is coupled to a third node common to the first and second transistors. A third MOS transistor has a first conduction electrode coupled to the gate of the first transistor and a second conduction electrode coupled to the gate of the second transistor.

Abstract translation: 电源开关包括在第一和第二节点之间串联的第一和第二MOS晶体管。 第一和第二晶体管都具有耦合到其衬底的栅极。 第一和第二电阻元件分别耦合在第一晶体管的栅极和第一节点之间，以及第二晶体管的栅极和第二节点之间。 三端双向可控硅开关元件耦合在第一和第二节点之间。 三端双向可控硅开关元件的栅极耦合到第一和第二晶体管共同的第三节点。 第三MOS晶体管具有耦合到第一晶体管的栅极的第一导电电极和耦合到第二晶体管的栅极的第二导电电极。

公开(公告)号：US20130057334A1

公开(公告)日：2013-03-07

申请号：US13669259

申请日：2012-11-05

Applicant: STMicroelectronics SA ,  ST Ericsson SA

Inventor： Frederic Hasbani ,  Pascal Urard ,  Fabrice Blisson ,  David Jacquet

IPC: H03K3/00

CPC classification number: H03K19/0016 ,  H03K19/0013 ,  H03K2217/0018

Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.

Abstract translation: 本公开中描述的实施例涉及一种用于为集成系统提供电力的方法，包括以下动作：向系统提供电源，接地和体偏置电压，体偏置电压包括p沟道MOS晶体管的体偏置电压， 大于或低于电源电压，以及n沟道MOS晶体管的体偏置电压低于或大于接地电压，根据系统的处理单元是否由系统提供的电压进行选择 在活动或不活动的时段期间，提供用于偏置处理单元的MOS晶体管的主体的电压，以及为处理单元的MOS晶体管的主体提供所选择的电压。