公开(公告)号：US10366896B2

公开(公告)日：2019-07-30

申请号：US15688852

申请日：2017-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.

公开(公告)号：US10361080B2

公开(公告)日：2019-07-23

申请号：US15641235

申请日：2017-07-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L21/3105 ,  H01L21/311 ,  H01L21/033 ,  H01L27/108 ,  H01L21/3213

Abstract: A patterning method is disclosed. A hard mask layer, a lower pattern transfer layer, an upper pattern transfer layer are formed on a target layer. A first SARP process is performed to pattern the upper pattern transfer layer into an upper pattern mask. A second SARP process is performed to pattern the lower pattern transfer layer into a lower pattern mask. The upper pattern mask and the lower pattern mask define hole patterns. The hole patterns is filled with a dielectric layer. The dielectric layer and the upper pattern mask are etched back until the lower pattern mask is exposed. The lower pattern mask is removed, thereby forming island patterns. Using the island patterns as an etching hard mask, the hard mask layer is patterned into hard mask patterns. Using the hard mask patterns as an etching hard mask, the target layer is patterned into target patterns.

公开(公告)号：US20190221655A1

公开(公告)日：2019-07-18

申请号：US15869087

申请日：2018-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Hsing Chen ,  Chun-Yu Chen ,  Chung-Ting Huang ,  Zih-Hsuan Huang ,  Yu-Chien Sung

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/033 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/66636 ,  H01L21/033 ,  H01L21/32139 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device is disclosed. A fin is formed on a substrate. The fin protrudes from a trench isolation layer on a substrate. The fin comprises a source region, a drain region and a channel region therebetween. A dummy gate strides across the fin and surrounding the channel region. An upper portion of the fin is removed so as to form a hollow channel underneath the dummy gate. A replacement channel layer is in-situ epitaxially grown in the hollow channel.

公开(公告)号：US20190221571A1

公开(公告)日：2019-07-18

申请号：US15885729

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Wei-Hsin Liu ,  Cheng-Hsu Huang ,  Jui-Min Lee ,  Yi-Wei Chen

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L27/10894 ,  H01L21/28556 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10897

Abstract: A semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.

公开(公告)号：US20190221570A1

公开(公告)日：2019-07-18

申请号：US15896091

申请日：2018-02-14

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Tzu-Chin Wu ,  Wei-Lun Hsu

IPC: H01L27/108 ,  H01L23/532

Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.

公开(公告)号：US10352986B2

公开(公告)日：2019-07-16

申请号：US15164129

申请日：2016-05-25

Applicant: United Microelectronics Corp.

Inventor： Hsin-Pang Lu ,  Hsin-Wen Chen

IPC: G05F1/56 ,  G01R31/26 ,  H01L49/02 ,  H01L27/092 ,  H01L21/8238

Abstract: A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned off. The method also includes detecting a voltage level of one of the doped well and the substrate to judge whether or not a voltage target is reached. The well power is turned on to apply the well voltage to the doped well when the voltage level as detected reaches to the voltage target.

公开(公告)号：US20190214465A1

公开(公告)日：2019-07-11

申请号：US15893681

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US20190214306A1

公开(公告)日：2019-07-11

申请号：US15885834

申请日：2018-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin

IPC: H01L21/8234 ,  H01L21/324 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.

公开(公告)号：US10347645B2

公开(公告)日：2019-07-09

申请号：US16207171

申请日：2018-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L27/11 ,  H01L27/12 ,  H01L23/535 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8234

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate comprises a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.

公开(公告)号：US10347640B1

公开(公告)日：2019-07-09

申请号：US16051508

申请日：2018-08-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ya-Ying Tsai ,  Keng-Jen Lin

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/06

Abstract: The invention provides a manufacturing method of a semiconductor device. First, a substrate is provided. A first recess and a second recess are formed in the substrate, a width of the first recess is smaller than a width of the second recess. Then, a first spin-on dielectric (SOD) layer is formed to fill the first recess and partially fill in the second recess, and then a first processing step is performed to transfer the first SOD layer into a first silicon oxide layer, a silicon nitride layer is subsequently formed on the first silicon oxide layer in the second recess, and then a second spin-on dielectric (SOD) layer is formed on the silicon nitride layer in the second recess, and a second processing step is performed to transfer the second SOD layer into a second silicon oxide layer.