公开(公告)号：US09459311B2

公开(公告)日：2016-10-04

申请号：US14306489

申请日：2014-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Vratislav Michal

IPC: G01R31/28 ,  H02M3/156 ,  H02M3/158 ,  G01R19/00 ,  G01R19/14 ,  G01R19/165 ,  H02M1/00 ,  G01R31/40

CPC classification number: G01R31/28 ,  G01R19/0092 ,  G01R19/14 ,  G01R19/16538 ,  G01R31/40 ,  H02M3/156 ,  H02M3/158 ,  H02M2001/0009

Abstract: A valley inductance current polarity change in a pulse width modulated circuit charged with an inductive charge is detected by comparing respective times that a first output of the circuit charged with an inductive charge and a second output of a pulse width modulated reference circuit with no inductive charge reach an output level. Responsive thereto, control over operation of the pulse width modulated circuit charged with an inductive charge is made with respect to switching to a pulse skipping mode of operation or keeping the pulse width modulation mode of operation.

Abstract translation: 通过比较充电感应电荷的电路的第一输出和脉冲宽度调制的参考电路的第二输出的感应电荷的电荷电流的波谷电感电流极性变化， 达到输出水平。 响应于此，对切换到脉冲跳过操作模式或保持脉冲宽度调制操作模式进行充电感应电荷的脉冲宽度调制电路的操作的控制。

公开(公告)号：US09401715B1

公开(公告)日：2016-07-26

申请号：US14718204

申请日：2015-05-21

Applicant: STMicroelectronics International N.V.

Inventor： Alok Kumar Tripathi ,  Priyankar Mathuria

IPC: H03K3/356 ,  H03K19/00

CPC classification number: H03K19/0013 ,  H03K3/012 ,  H03K3/356173

Abstract: An electronic device includes a pulsed latch circuit configured to latch a data input signal to an output based upon receipt of a pulse signal. A pulse generation circuit is configured to compare the data input signal and an output signal at the output of the pulsed latch circuit, and to generate the pulse signal based upon a mismatch therebetween in response to a clock signal.

Abstract translation: 电子设备包括脉冲锁存电路，其被配置为基于接收到脉冲信号将数据输入信号锁存到输出端。 脉冲发生电路被配置为将数据输入信号和脉冲锁存电路的输出端的输出信号进行比较，并且响应于时钟信号，基于它们之间的失配产生脉冲信号。

公开(公告)号：US09391769B2

公开(公告)日：2016-07-12

申请号：US14509377

申请日：2014-10-08

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics International N.V

Inventor： Julien Saade ,  Abdelaziz Goulahsen

IPC: H04L29/06 ,  H04L9/00 ,  H04L25/03

CPC classification number: H04L9/001 ,  H04L25/03 ,  H04L25/03866 ,  H04L2209/34

Abstract: A method for transmitting data in series includes producing a scrambled signal by applying a scrambling using a pseudo-random sequence to an incoming serial signal conveying the data and producing an outgoing serial signal from the scrambled signal. After each sequence of N consecutive bits at the same state in the scrambled signal, a dummy bit of reverse state is inserted in the outgoing signal.

公开(公告)号：US09385593B2

公开(公告)日：2016-07-05

申请号：US14482714

申请日：2014-09-10

Applicant: STMicroelectronics International N.V.

Inventor： Shyam Somayajula ,  Sri Ram Gupta ,  Lionel Cimaz

IPC: H04R3/00 ,  H03F3/217 ,  H02M3/07 ,  H03F3/187 ,  H03F3/45 ,  H02M1/00

CPC classification number: H02M3/07 ,  H02M2001/0032 ,  H02M2001/0035 ,  H03F3/187 ,  H03F3/45475 ,  H03F2200/03 ,  Y02B70/16

Abstract: A device may be associated with a power source. The device may include a charge pump configured to output a pulse-width modulated voltage based upon an input voltage from the power source, with the pulse-width modulated voltage varying between a first voltage and a second voltage. The device may also include a low-pass filter comprising an output capacitor, with the output capacitor being configured to average the pulsed-width modulated voltage and to output a filtered voltage having a value different than that of the input voltage. The device may further include a controller configured to selectively decouple the charge pump from the power source when a load imposed on the low-pass filter is below a threshold load.

Abstract translation: 设备可以与电源相关联。 该装置可以包括电荷泵，其被配置为基于来自电源的输入电压输出脉宽调制电压，其中脉宽调制电压在第一电压和第二电压之间变化。 器件还可以包括包括输出电容器的低通滤波器，输出电容器被配置为平均脉冲宽度调制电压并输出具有与输入电压值不同的值的滤波电压。 该装置还可以包括控制器，其被配置为当施加在低通滤波器上的负载低于阈值负载时，选择性地将电荷泵与电源分离。

公开(公告)号：US20160187765A1

公开(公告)日：2016-06-30

申请号：US14584080

申请日：2014-12-29

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tzvi Philipp

IPC: G03B21/14 ,  G02B27/00 ,  G03B21/28 ,  G02B26/08 ,  G02B17/08

CPC classification number: G03B21/147 ,  G02B17/0852 ,  G02B17/0896 ,  G02B26/0816 ,  G02B27/0068 ,  G03B21/142 ,  G03B21/28 ,  H04N9/317 ,  H04N9/3173

Abstract: An electronic device includes a movable mirror system to selectively reflect an incident image projection beam traveling along a first path toward a second path different than a first path. The image projection beam displays a corrected image at a first location but would otherwise display an uncorrected image at a second location when the movable mirror system reflects the image projection beam toward the second path. The electronic device also includes an optical correction system having at least one corrective optic element to correct the image projection beam to display a corrected image at the second location when the movable mirror system reflects the image projection beam toward the second path.

Abstract translation: 电子设备包括可移动镜系统，用于选择性地将沿着第一路径行进的入射图像投影光束朝向与第一路径不同的第二路径反射。 图像投影光束在第一位置显示校正图像，但是当可移动反射镜系统将图像投影光束朝向第二路径反射时，否则将在第二位置处显示未校正的图像。 电子设备还包括光学校正系统，其具有至少一个校正光学元件，以在可移动镜像系统将图像投射束朝向第二路径反射时校正图像投影光束以在第二位置显示校正图像。

公开(公告)号：US09378779B2

公开(公告)日：2016-06-28

申请号：US14329747

申请日：2014-07-11

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Amit Chhabra

IPC: G11C5/14 ,  G05F1/46

CPC classification number: G11C5/148 ,  G05F1/46 ,  G05F1/465 ,  H03K3/0377 ,  H03K5/082 ,  H03K17/223

Abstract: A dual-rail memory circuit having a sleep generation circuit configured to prevent undesired currents from being generated during power-up and while transitioning power states. When a dual-rail memory circuit is powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in a dual-rail memory circuit may be used to precisely control an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.

Abstract translation: 具有睡眠产生电路的双轨存储器电路，其被配置为防止在上电期间和在转换功率状态期间产生不期望的电流。 当双轨存储器电路上电或从睡眠模式退出时，各种电源节点的升高可以以不同的速率发生。 因此，在双轨存储器电路中，第一电压轨可以在第二电压轨之前处于电压。 这种瞬时的操作状态可能导致电流尖峰不必要地抽取功率并引入不期望的低效率。 双轨存储器电路中的内部睡眠信号产生电路可以用于精确地控制内部睡眠信号，使得从关闭或休眠模式到操作模式的转变被设置为确保电源电压节点足够接近于at - 释放睡眠模式前的电压工作电平。

公开(公告)号：US20160181978A1

公开(公告)日：2016-06-23

申请号：US14576535

申请日：2014-12-19

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Gauri Mittal ,  Kallol Chatterjee ,  Pallavi Muktesh ,  Nitin Jain ,  Pradeep Kumar Badrathwal

IPC: H03B5/36

CPC classification number: H03B5/364 ,  H03B5/366 ,  H03B2200/0012 ,  H03B2200/0038

Abstract: A circuit includes an oscillator circuit to receive a bias current and generate an oscillating signal at an output node. A current differencing circuit subtracts a current at the output node from a reference current to generate a first current. In addition, a current mirroring circuit mirrors the first current to generate the bias current. An inverter stage is coupled to the output node, and includes an input branch configured to receive the oscillating signal and generate first and second control signals based upon the oscillating signal. At least one amplifying branch receives the first and second control signals and amplifies the first and second control signals. An output branch receives the amplified first and second control signals and generates an amplified version of the oscillating signal based upon the amplified first and second control signals.

Abstract translation: 电路包括用于接收偏置电流并在输出节点产生振荡信号的振荡器电路。 电流差分电路从参考电流中减去输出节点处的电流以产生第一电流。 此外，电流镜像电路反射第一电流以产生偏置电流。 逆变器级耦合到输出节点，并且包括被配置为接收振荡信号并基于振荡信号产生第一和第二控制信号的输入分支。 至少一个放大支路接收第一和第二控制信号并放大第一和第二控制信号。 输出分支接收放大的第一和第二控制信号，并且基于放大的第一和第二控制信号产生振荡信号的放大版本。

公开(公告)号：US09361117B2

公开(公告)日：2016-06-07

申请号：US14266010

申请日：2014-04-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics International N.V.

Inventor： Ankur Behl ,  Gregory Poivre

IPC: G06F1/00 ,  G06F1/04 ,  G06F9/44 ,  G11C16/32 ,  G11C7/10 ,  G11C7/22 ,  G11C16/04 ,  G06F1/10 ,  G06F1/08

CPC classification number: G06F9/44 ,  G06F1/08 ,  G06F1/10 ,  G06F9/4401 ,  G06F9/4403 ,  G11C7/1072 ,  G11C7/222 ,  G11C16/0416 ,  G11C16/32

Abstract: Embodiments disclosed herein generally relate for efficiently retrieving boot code for a processor from serial NOR flash memory. When a boot code request is received, a request handler in data capture logic tags successive address read requests to indicate whether the requests indicate contiguous addresses in the NOR flash memory for the boot code. Different circuitry in the data capture logic operates on different mesochronous clock signals. One clock signal drives the capture of boot code from NOR flash, and the other controls synchronized tagging, storing, pre-fetching, and transmitting of the captured boot code data.

Abstract translation: 本文公开的实施例通常涉及从串行NOR闪速存储器有效地检索处理器的引导代码。 当接收到引导代码请求时，数据捕获逻辑中的请求处理器标记连续的地址读取请求，以指示请求是否指示用于引导代码的NOR闪存中的连续地址。 数据采集​​逻辑中的不同电路在不同的同步时钟信号上运行。 一个时钟信号驱动从NOR闪存捕获引导代码，另一个控制器同步标记，存储，预取和发送捕获的引导代码数据。

公开(公告)号：US20160078815A1

公开(公告)日：2016-03-17

申请号：US14797354

申请日：2015-07-13

Applicant: STMicroelectronics International N.V.

Inventor： Jerome Nebon ,  Jean-Marie Permezel

IPC: G09G3/32

CPC classification number: G09G3/3258 ,  G09G3/3225 ,  G09G2300/0413 ,  G09G2320/0247 ,  G09G2320/0261 ,  G09G2320/043 ,  G09G2340/0435 ,  G09G2360/147

Abstract: A device includes an OLED pixel and a control circuit controlled at a refresh rate thereof. The device includes first and second dummy control circuits having similar operating characteristics to the control circuit. A controller and logic circuit switch on the first and second dummy control circuits and apply an input voltage so the first and second dummy control circuits output first and second output voltages. At a first time, the controller and logic circuit switch off the second dummy control circuit so a leakage current flows through the second dummy control circuit to ground, causing the second output voltage to reduce. Comparison circuitry determines a second time at which, due to the reduction of the second output voltage, a difference between the first and second output voltages is greater than a threshold. Determination circuitry determines the refresh frequency based upon elapsed time between the first and second times.

Abstract translation: 一种器件包括OLED像素和以其刷新率控制的控制电路。 该装置包括具有与控制电路相似的工作特性的第一和第二虚拟控制电路。 控制器和逻辑电路在第一和第二虚拟控制电路上开关并施加输入电压，使得第一和第二虚拟控制电路输出第一和第二输出电压。 第一次，控制器和逻辑电路关闭第二虚拟控制电路，使得漏电流通过第二虚拟控制电路流到地，从而使第二输出电压降低。 比较电路确定第二时间，由于第二输出电压的减小，第一和第二输出电压之间的差大于阈值。 确定电路基于第一次和第二次之间的经过时间来确定刷新频率。

公开(公告)号：US20160056921A1

公开(公告)日：2016-02-25

申请号：US14931331

申请日：2015-11-03

Applicant: STMicroelectronics International N.V.

Inventor： Achraf Dhayni ,  Hussein Hijazi

IPC: H04L1/00 ,  H04B7/04

CPC classification number: H04L1/0054 ,  H04B7/0413 ,  H04L1/0631 ,  H04L25/03197 ,  H04L25/03242 ,  H04L25/03961 ,  H04L2025/03414 ,  H04L2025/0342 ,  H04L2025/03426

Abstract: A receiver estimates a vector of emitted symbols over a MIMO transmission channel which is emitted by emitting antennas. The receiver receives a vector of received symbols on receiving antennas. Estimation of the vector of emitted symbols is made by calculating a metric associated with a criterion for each vector of a subset of all possible vectors of emitted symbols and selecting an estimation for said vector of emitted symbols as the vector of emitted symbols among said subset which minimizes said metric.

Abstract translation: 接收机估计由发射天线发射的MIMO传输信道上的发射码元的向量。 接收机在接收天线上接收接收符号的向量。 通过计算与发射符号的所有可能向量的子集的每个向量的标准相关联的度量来估计发射符号的向量，并且将所发射的符号的所述向量的估计选择为所述子集中的发射符号的向量， 最小化所述度量。