公开(公告)号：US07120072B2

公开(公告)日：2006-10-10

申请号：US10881001

申请日：2004-06-30

Applicant: Yibin Ye ,  Dinesh Somasekhar ,  Muhammad M Khellah ,  Fabrice Paillet ,  Stephen H Tang ,  Ali Keshavarzi ,  Shih-Lien L Lu ,  Vivek K De

Inventor： Yibin Ye ,  Dinesh Somasekhar ,  Muhammad M Khellah ,  Fabrice Paillet ,  Stephen H Tang ,  Ali Keshavarzi ,  Shih-Lien L Lu ,  Vivek K De

IPC: G11C7/00

CPC classification number: G11C11/405

Abstract: A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.

Abstract translation: 双晶体管存储单元包括写晶体管和读晶体管。 读取存储单元时，读取晶体管导通，读取位线上产生电压。

公开(公告)号：US07110278B2

公开(公告)日：2006-09-19

申请号：US10954537

申请日：2004-09-29

Applicant: Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

Inventor： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

IPC: G11C17/08

CPC classification number: G11C17/16

Abstract: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.

Abstract translation: 公开了利用一次可编程反熔丝电池的交叉点存储器阵列。

公开(公告)号：US07098507B2

公开(公告)日：2006-08-29

申请号：US10879480

申请日：2004-06-30

Applicant: Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Brian Doyle ,  Suman Datta ,  Vivek K. De

Inventor： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Brian Doyle ,  Suman Datta ,  Vivek K. De

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/39

CPC classification number: H01L29/785 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7841

Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

公开(公告)号：US20060140041A1

公开(公告)日：2006-06-29

申请号：US11027696

申请日：2004-12-28

Applicant: Arman Vassighi ,  Ali Keshavarzi ,  Vivek De

Inventor： Arman Vassighi ,  Ali Keshavarzi ,  Vivek De

IPC: G11C8/00

CPC classification number: G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

Abstract: A thermal feedback loop controls leakage current during burn-in of a circuit.

Abstract translation: 热反馈回路控制电路老化期间的漏电流。

公开(公告)号：US07061806B2

公开(公告)日：2006-06-13

申请号：US10954931

申请日：2004-09-30

Applicant: Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

Inventor： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C11/4076 ,  G11C2216/14

Abstract: A system to write to a plurality of memory cells coupled to a word line, each of the plurality of memory cells comprising a transistor having a source, a drain, a body and a gate coupled to the word line. Some embodiments provide biasing of one or more of the plurality of memory cells in saturation to inject charge carriers into the body of the one or more of the plurality of memory cells, and biasing of each of the plurality of memory cells in accumulation to tunnel charge carriers from the body of each of the plurality of memory cells to the gate of each of the plurality of memory cells.

Abstract translation: 一种写入耦合到字线的多个存储单元的系统，所述多个存储器单元中的每一个包括具有耦合到所述字线的源极，漏极，主体和栅极的晶体管。 一些实施例提供饱和中的多个存储单元中的一个或多个的偏置以将电荷载流子注入多个存储单元中的一个或多个存储器单元的主体中，并且将多个存储单元中的每一个的累积偏压到隧道电荷 载体从多个存储单元的每一个的主体到多个存储单元中的每一个的门。

公开(公告)号：US20060067152A1

公开(公告)日：2006-03-30

申请号：US10954537

申请日：2004-09-29

Applicant: Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

Inventor： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

IPC: G11C17/18 ,  G11C5/06

CPC classification number: G11C17/16

Abstract: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.

公开(公告)号：US20060067133A1

公开(公告)日：2006-03-30

申请号：US10956407

申请日：2004-09-30

Applicant: Yibin Ye ,  Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Gerhard Schrom ,  Vivek De

Inventor： Yibin Ye ,  Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Gerhard Schrom ,  Vivek De

IPC: G11C7/10

CPC classification number: G11C11/404 ,  G11C2211/4016

Abstract: A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.

Abstract translation: 用于单相写入单晶体管存储单元阵列的方法和装置。 在一个实施例中，该方法包括对存储器单元阵列的选定字线的单相写入。 一旦选择了字线，逻辑零值被存储在存储单元阵列的选定字线的至少一个存储单元中。 同时，逻辑0值存储在所选择的存储单元阵列的选定字线的至少一个存储单元中。 描述和要求保护其他实施例。

公开(公告)号：US20060014331A1

公开(公告)日：2006-01-19

申请号：US10879480

申请日：2004-06-30

Applicant: Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

Inventor： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

IPC: H01L21/84

CPC classification number: H01L29/785 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7841

Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

Abstract translation: 浮体动态随机存取存储器件可以包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。 可以在半导体主体的顶表面和半导体本体的横向相对的侧壁上形成栅介质层。 栅极电极可以形成在半导体本体的顶表面上的栅极电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。 栅电极可能仅部分地耗尽半导体本体的区域，并且部分耗尽的区域可以用作逻辑状态的存储节点。

公开(公告)号：US06903984B1

公开(公告)日：2005-06-07

申请号：US10748222

申请日：2003-12-31

Applicant: Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De

Inventor： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De

IPC: G11C11/404 ,  G11C11/408 ,  H01L27/108 ,  H01L29/78 ,  G11C7/00

CPC classification number: H01L27/108 ,  G11C11/404 ,  G11C11/4085 ,  H01L29/7841

Abstract: A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.

Abstract translation: DRAM存储单元使用单个晶体管来执行常规单元的数据存储和切换功能。 晶体管具有浮置通道体，其存储对应于两个数字数据值之一的电位。 晶体管还包括连接到第一字线的栅极，连接到第二字线的漏极和连接到位线的源极。 通过将单词和位线设置为特定的电压状态，通道体由于碰撞电离而存储数字一个电位，并且由于体对源结的正向偏置而存储数字零值。

公开(公告)号：US06828638B2

公开(公告)日：2004-12-07

申请号：US09469406

申请日：1999-12-22

Applicant: Ali Keshavarzi ,  Vivek K. De ,  Tanay Karnik ,  Rajendran Nair

Inventor： Ali Keshavarzi ,  Vivek K. De ,  Tanay Karnik ,  Rajendran Nair

IPC: H01L2976

CPC classification number: H01L27/0805 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.

Abstract translation: 在一些实施例中，本发明涉及具有承载电源电压的第一导体和承载接地电压的第二导体的管芯。 以耗尽模式工作的半导体电容器耦合在第一和第二导体之间，以在第一和第二导体之间提供去耦电容，半导体电容器具有栅极电压。 可以使用各种构造，包括：n体中的n +栅极多晶硅和n +源极/漏极区域; p +栅极多晶硅和n +源极/漏极区域; p +栅极poly和p +源极/漏极区域在n体中; p体中的p +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和n +源极/漏极区域。 电源电压可能比平带电压具有更大的绝对值。