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    Decoupling capacitors for thin gate oxides
    1.
    发明授权
    Decoupling capacitors for thin gate oxides 有权
    薄栅氧化物去耦电容器

    公开(公告)号：US06828638B2

    公开(公告)日：2004-12-07

    申请号：US09469406

    申请日：1999-12-22

    Applicant: Ali Keshavarzi ,  Vivek K. De ,  Tanay Karnik ,  Rajendran Nair

    Inventor： Ali Keshavarzi ,  Vivek K. De ,  Tanay Karnik ,  Rajendran Nair

    IPC: H01L2976

    CPC classification number: H01L27/0805 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.

    Abstract translation: 在一些实施例中，本发明涉及具有承载电源电压的第一导体和承载接地电压的第二导体的管芯。 以耗尽模式工作的半导体电容器耦合在第一和第二导体之间，以在第一和第二导体之间提供去耦电容，半导体电容器具有栅极电压。 可以使用各种构造，包括：n体中的n +栅极多晶硅和n +源极/漏极区域; p +栅极多晶硅和n +源极/漏极区域; p +栅极poly和p +源极/漏极区域在n体中; p体中的p +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和n +源极/漏极区域。 电源电压可能比平带电压具有更大的绝对值。

    Voltage dependent capacitor configuration for higher soft error rate tolerance
    3.
    发明授权
    Voltage dependent capacitor configuration for higher soft error rate tolerance 有权
    电压相关电容器配置，用于更高的软错误率容差

    公开(公告)号：US06552887B1

    公开(公告)日：2003-04-22

    申请号：US09608457

    申请日：2000-06-29

    Applicant: Tanay Karnik ,  Rajendran Nair ,  Vivek K. De

    Inventor： Tanay Karnik ,  Rajendran Nair ,  Vivek K. De

    IPC: G11C1140

    CPC classification number: G11C5/005 ,  G11C11/401 ,  H01L27/0808

    Abstract: A voltage dependent capacitor to provide soft error rate tolerance in an integrated circuit is disclosed. In one embodiment, a parallel n-p voltage dependent capacitor is used to protect a node from noise. In another embodiment, an nFET-in-nWell voltage dependent capacitor is used to provide a soft error rate tolerant capacitor with reduced area.

    Abstract translation: 公开了一种用于在集成电路中提供软错误率容限的电压相关电容器。 在一个实施例中，使用并联n-p电压依赖电容器来保护节点免受噪声。 在另一个实施例中，使用nFET-nWell电压相关电容器来提供具有减小的面积的软误差容限电容器。

    Memory cell driver circuits
    4.
    发明授权
    Memory cell driver circuits 有权
    存储单元驱动电路

    公开(公告)号：US07236410B2

    公开(公告)日：2007-06-26

    申请号：US11169106

    申请日：2005-06-27

    Applicant: Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Vivek K. De

    Inventor： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Vivek K. De

    IPC: G11C7/00 ,  G11C17/00 ,  G11C5/06

    CPC classification number: G11C17/18

    Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

    Abstract translation: 系统包括用于对存储器单元进行编程的上拉电路。 上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍， 并产生第二控制信号和共源共栅级。 共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道 电压和输出节点以提供单元编程信号。

    Method and apparatus for weak inversion mode MOS decoupling capacitor
    5.
    发明授权
    Method and apparatus for weak inversion mode MOS decoupling capacitor 失效
    弱反转模式MOS去耦电容器的方法和装置

    公开(公告)号：US06849909B1

    公开(公告)日：2005-02-01

    申请号：US09677698

    申请日：2000-09-28

    Applicant: Rajendran Nair ,  Siva G. Narendra ,  Tanay Karnik ,  Vivek K. De

    Inventor： Rajendran Nair ,  Siva G. Narendra ,  Tanay Karnik ,  Vivek K. De

    IPC: H01L27/08 ,  H01L31/119 ,  H01L29/088 ,  H01L29/90

    CPC classification number: H01L27/0811 ,  Y10S257/901

    Abstract: A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from that commonly used. In one exemplary embodiment, platinum silicate (PtSi) is used. In alternate embodiments, the threshold voltage of the PMOS transistor may be changed by modifying the dopant levels of the substrate. In either embodiment the flat band magnitude of the transistor is shifted by the change in materials used to construct the transistor. When such a transistor is connected with the gate lead connected to the positive supply voltage and the other leads connected to the negative (ground) supply voltage, an improved decoupling capacitor results.

    Abstract translation: 描述了用于提供弱反型模式金属氧化物半导体（MOS）去耦电容器的方法和装置。 在一个实施例中，增强型p沟道MOS（PMOS）晶体管由其功能与常用功能不同的栅极材料构成。 在一个示例性实施方案中，使用铂硅酸盐（PtSi）。 在替代实施例中，可以通过修改衬底的掺杂剂水平来改变PMOS晶体管的阈值电压。 在任一实施例中，晶体管的平带幅度偏移用于构造晶体管的材料的变化。 当这种晶体管与连接到正电源电压的栅极引线连接，而其他引线连接到负（接地）电源电压时，会产生改进的去耦电容。

    APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY
    6.
    发明申请
    APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY 失效
    用于编程存储阵列的装置和方法

    公开(公告)号：US20060285393A1

    公开(公告)日：2006-12-21

    申请号：US11158518

    申请日：2005-06-21

    Applicant: Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De ,  Tanay Karnik

    Inventor： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De ,  Tanay Karnik

    IPC: G11C16/04

    CPC classification number: G11C17/18

    Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.

    Abstract translation: 提供了一种对存储器阵列进行编程的方法，包括通过相对于各个字线相互依次提供多个电压步骤来访问存储器阵列的多个字线，以及每个存储器阵列的多个位线 访问相应字线的时间，对与同时访问的各个字和位线相对应的多个设备进行编程，每个设备通过断开设备的介电层进行编程，访问位线被排序，使得只有 一个设备中的单个设备一次被编程。

    Memory cell driver circuits
    8.
    发明申请
    Memory cell driver circuits 有权
    存储单元驱动电路

    公开(公告)号：US20060291265A1

    公开(公告)日：2006-12-28

    申请号：US11169106

    申请日：2005-06-27

    Applicant: Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad Khellah ,  Vivek De

    Inventor： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad Khellah ,  Vivek De

    IPC: G11C17/00

    CPC classification number: G11C17/18

    Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

    Abstract translation: 系统包括用于对存储器单元进行编程的上拉电路。 上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍， 并产生第二控制信号和共源共栅级。 共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道 电压和输出节点以提供单元编程信号。

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