Abstract:
A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method may include simultaneously forming at least one via and at least one upper capacitor plate opening in a first dielectric layer having an underlying cap dielectric layer deposited over a first material region having a first conductive material within a conductive region and forming a trench above the via. The underlying cap dielectric layer may be modified in a way that increases its dielectric constant as a result of simultaneously be heated by a heat source and impinged with and energy beam. The method may also include filling the via, trench, and upper capacitor plate opening with a second conductive material resulting in an integrated circuit structure and employing CMP to remove any excess second conductive material from the integrated circuit structure.
Abstract:
A birefringent device has a polarization separating device configured to separate a first composite light beam into first and second components thereof. The first and second components are orthogonally polarized with respect to one another. A first path is configured to transmit the first component and has a first optical path length. Similarly, a second path is configured to transmit the second component and has a second optical path length. The second optical path length is different from the first optical path length. A polarization combining device is configured to recombine the first and second components so as to form a second composite light beam. The second composite light beam is birefringent with respect to the first composite light beam.
Abstract:
A low dispersion comb filter or interleaver assembly has a first interleaver element and a second interleaver element. The first interleaver element is configured so as to provide a dispersion vs. wavelength curve wherein each dispersion value thereof is approximately opposite in value to a dispersion value at the same wavelength for the second interleaver element, so as to mitigate net or total dispersion in the interleaver assembly.
Abstract:
A low dispersion comb filter or interleaver comprises a first birefringent element assembly having at least one birefringent element and a second birefringent element assembly having at least one other birefringent element. The first birefringent element assembly and the second birefringent element assembly are configured so as to cooperate with one another in a manner which mitigates dispersion of the interleaver. By aligning the polarization directions of the odd channels and the even channels so as to be parallel with respect to one another prior to entering the second birefringent element assembly, zero or nearly zero dispersion is obtained simultaneously for both the odd and even channels.
Abstract:
A distributed collaborative computer system is provided that comprises a plurality of server computers interconnected via a high-speed link. Client computers can connect to any available server computer and start or join a conference hosted on either the server computer to which the client computer is connected or any other server in the system. As a result, the system and method of the present invention is easily scalable to support an arbitrary number of participants to a conference by merely adding the appropriate number of server computers to the system. In addition, by replicating the conference information on more than one server computer, the single point of failure limitation is eliminated. In fact, if a server hosting or participating in a conference malfunctions, the failure is detected by other server computers and the client computer is able to reconnect to the conference through a new server computer.
Abstract:
An interleaver has a birefringent element assembly and a reflector configured so as to direct light from the birefringent element assembly back into and through birefringent element assembly. The birefringent element assembly has at least one birefringent element. Directing light from the birefringent element assembly back through the birefringent element assembly enhances transmission characteristics and/or mitigates dispersion.
Abstract:
An improved microelectronic structure is disclosed. The improved structure includes an air-gap region formed by removing an insulating material through an aperture residing in a mask.
Abstract:
An interconnect fabrication process and structure provides barrier enhancement at the via sidewalls and improved capability to fabricate high aspect ratio dual damascene interconnects. A via structure is patterned into the via dielectric first, then a dielectric barrier (for example, anisotropically etched silicon nitride) is formed only along the via sidewalls in the dual damascene structure prior to deposition of a metal barrier (for example, Ta/TaN). In this way, the effective barrier thickness along the bottom of the via is increased, eliminating the structure's susceptibility to metal migration. The absence of dielectric barrier along the interconnect trench sidewalls leads to low interconnect resistance and low interconnect capacitance. The present invention also provides an improved fabrication method for obtaining high aspect ratio dual damascene interconnect structures.
Abstract:
An interconnect structure and fabrication method are provided to form air gaps between interconnect lines and between interconnect layers. A conductive material is deposited and patterned to form a first level of interconnect lines. A first dielectric layer is deposited over the first level of interconnect lines. One or more air gaps are formed in the first dielectric layer to reduce inter-layer capacitance, intra-layer capacitance or both inter-layer and intra-layer capacitance. At least one support pillar remains in the first dielectric layer to promote mechanical strength and thermal conductivity. A sealing layer is deposited over the first insulative layer to seal the air gaps. Via holes are patterned and etched through the sealing layer and the first dielectric layer. A conductive material is deposited to fill the via holes and form conductive plugs therein. Thereafter, a conductive material is deposited and patterned to form a second level of interconnect lines.
Abstract:
A copper bonding pad is directly supported by a copper via pad structure, the copper via pad structure having substantially the same geometry and dimensions as the copper bonding pad. The combination of the copper bonding pad and the copper via pad structure results in an increase in effective thickness of the copper bonding pad. Due to this effective increase in the bonding pad thickness, the bonding pad is more tolerant to the potential dishing problem caused by the CMP process. Additional metal pad structures and via pad structures are used below the bonding pad. The additional metal pad structures and via pad structures comprise alternating segments of interconnect metal and dielectric fillers, and alternating segments of via metal and dielectric fillers, respectively. The alternating segments of interconnect metal and dielectric fillers and the alternating segments of via metal and dielectric fillers prevent or reduce the potential dishing problem that otherwise exists in damascene and CMP processing. The alternating segments of interconnect metal and dielectric fillers and the alternating segments of via metal and dielectric fillers are arranged such that there are a number of columns of solid metal support under the bonding pad. The columns of solid metal support significantly improve the poor mechanical support otherwise provided by the low dielectric constant materials that are presently used in fabrication of modern copper integrated circuits. The columns of solid metal support also improve thermal conductivity of the bonding pad.