公开(公告)号：US06566270B1

公开(公告)日：2003-05-20

申请号：US09662677

申请日：2000-09-15

Applicant: Wei Liu ,  Scott Williams ,  Stephen Yuen ,  David Mui ,  Meihua Shen

Inventor： Wei Liu ,  Scott Williams ,  Stephen Yuen ,  David Mui ,  Meihua Shen

IPC: H01L21302

CPC classification number: H01L21/3065

Abstract: A method for processing a substrate disposed in a substrate process chamber having a source power includes transferring the substrate into the substrate process chamber. A trench is etched on the substrate by exposing the substrate to a plasma formed from a first etchant gas by applying RF energy from the source power system and biasing the plasma toward the substrate. Byproducts adhering to inner surfaces of the substrate process chamber are removed by igniting a plasma formed from a second etchant gas including a halogen source in the substrate process chamber without applying bias power or applying minimal bias power. Thereafter, the substrate is removed from the chamber. At least 100 more substrates are processed with the etching-a-trench step and removing-etch-byproducts step before performing a dry clean or wet clean operation on the chamber.

Abstract translation: 用于处理设置在具有源功率的基板处理室中的基板的方法包括将基板转移到基板处理室中。 通过从源功率系统施加RF能量并将等离子体偏压到衬底，将衬底暴露于由第一蚀刻剂气体形成的等离子体上，在衬底上蚀刻沟槽。 通过在不施加偏置功率或施加最小偏压功率的情况下点燃由包括卤素源的第二蚀刻剂气体在衬底处理室中形成的等离子体而去除附着于衬底处理室的内表面的副产物。 此后，将基板从腔室中取出。 在对腔室进行干洗或湿清洁操作之前，至少用100个蚀刻a沟槽步骤和去除蚀刻副产物步骤处理多个衬底。

公开(公告)号：US06458671B1

公开(公告)日：2002-10-01

申请号：US09784997

申请日：2001-02-16

Applicant: Wei Liu ,  David Mui

Inventor： Wei Liu ,  David Mui

IPC: H01L2120

CPC classification number: H01L27/10861 ,  H01L21/76232

Abstract: A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device. The method comprises: (1) providing a trench capacitor structure comprising (a) a silicon substrate having an upper and a lower surface; (b) first and second trenches extending from the upper surface into the silicon substrate; (c) first and second oxide regions lining at least portions of the first and second trenches; and (d) first and second polysilicon regions at least partially filling the oxide lined first and second trenches; and (2) forming a shallow trench from an upper surface of the structure, the shallow trench having a substantially flat trench bottom that forms an interface with portions of the silicon substrate, the first oxide region, the second oxide region, the first polysilicon region and the second polysilicon region, the shallow trench being formed by a process comprising (a) a first plasma etching step having an oxide:silicon:polysilicon selectivity of 1:1:1, more preferably >1.3:1:1.

公开(公告)号：US06449698B1

公开(公告)日：2002-09-10

申请号：US09383743

申请日：1999-08-26

Applicant: Sanjay Raghunath Deshpande ,  David Mui ,  Praveen S. Reddy

Inventor： Sanjay Raghunath Deshpande ,  David Mui ,  Praveen S. Reddy

IPC: G06F1200

CPC classification number: G06F12/0862 ,  G06F12/0888 ,  G06F2212/6022

Abstract: A method and system for bypassing a prefetch data path is provided. Each transaction within a system is tagged, and as transactions are issued for retrieving data, the system has a data prefetch unit for prefetching data from a processor, a memory subsystem, or an I/O agent into a prefetch data buffer. A prefetch data buffer entry is allocated for a data prefetch transaction, and the data prefetch transaction is issued. While the prefetch transaction is pending, a read transaction is received from a transaction requestor. The address for the read transaction is compared with the addresses of the pending data prefetch transactions, and in response to an address match, the prefetch data buffer entry for the matching prefetch transaction is checked to determine whether data has been received for the data prefetch transaction. In response to a determination that data has not been received for the data prefetch transaction, the prefetch data buffer entry is deallocated, and the transaction tag for the data prefetch transaction is stored in a table for bypassing a prefetch data path. When data for a data prefetch transaction is received, its transaction tag is compared with transaction tags in the table for bypassing the prefetch data path, and in response to a transaction tag match, the received data is sent to the transaction requestor.

Abstract translation: 提供了一种用于绕过预取数据路径的方法和系统。 系统内的每个事务被标记，并且当发出用于检索数据的事务时，系统具有用于将数据从处理器，存储器子系统或I / O代理预取到预取数据缓冲器中的数据预取单元。 为数据预取事务分配预取数据缓冲区条目，并发出数据预取事务。 在预取事务处于待处理状态的同时，从事务请求者接收到读取事务。 将读取事务的地址与待处理的数据预取事务的地址进行比较，并且响应于地址匹配，检查用于匹配预取事务的预取数据缓冲器条目以确定是否已经为数据预取事务接收了数据 。 响应于对数据预取事务尚未接收到数据的确定，取消预取数据缓冲器条目，并且用于数据预取事务的事务标签存储在用于绕过预取数据路径的表中。 当接收到用于数据预取事务的数据时，其交易标签与表中的交易标签进行比较，以绕过预取数据路径，并且响应于事务标签匹配，所接收的数据被发送到事务请求者。

公开(公告)号：US09772851B2

公开(公告)日：2017-09-26

申请号：US11923709

申请日：2007-10-25

Applicant: Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

Inventor： Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

IPC: G06F9/40 ,  G06F1/32 ,  G06F9/38 ,  G06F9/32 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3802 ,  G06F1/3234 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method, system, and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycles of the single branch, backwards short loop, rather than from the instruction cache.

公开(公告)号：US09395995B2

公开(公告)日：2016-07-19

申请号：US13408739

申请日：2012-02-29

Applicant: Ronald Hall ,  Michael L Karm ,  Brian R Mestan ,  David Mui

Inventor： Ronald Hall ,  Michael L Karm ,  Brian R Mestan ,  David Mui

IPC: G06F9/40 ,  G06F1/32 ,  G06F9/38 ,  G06F9/32

CPC classification number: G06F9/3802 ,  G06F1/3234 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method, system, and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycles of the single branch, backwards short loop, rather than from the instruction cache.

Abstract translation: 一种用于在处理器指令单元内指令取出的方法，系统和计算机程序产品，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。 修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 处理器的指令单元中的指令取出在单个分支，向后的短循环的循环周期内，而不是从指令高速缓存中，从修改的缓冲器中检索短循环的指令。

公开(公告)号：US09052910B2

公开(公告)日：2015-06-09

申请号：US12132517

申请日：2008-06-03

Applicant: Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

Inventor： Ronald Hall ,  Michael L. Karm ,  Brian R. Mestan ,  David Mui

IPC: G06F9/38

CPC classification number: G06F9/381 ,  G06F9/3814 ,  G06F9/3851

Abstract: A design structure provides instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.

Abstract translation: 设计结构提供了处理器指令单元内的指令获取，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。 修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。 指令在循环周期长度存储在修改后的指令缓冲区中。 处理器指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

公开(公告)号：US08758522B2

公开(公告)日：2014-06-24

申请号：US13115649

申请日：2011-05-25

Applicant: Ji Zhu ,  Arjun Mendiratta ,  David Mui

Inventor： Ji Zhu ,  Arjun Mendiratta ,  David Mui

IPC: B08B3/02

CPC classification number: C11D7/5009 ,  C11D3/3723 ,  C11D3/3765 ,  C11D3/3773 ,  C11D7/261 ,  C11D7/3263 ,  C11D7/34 ,  C11D11/0047 ,  H01L21/02057 ,  H01L21/67051 ,  Y10S134/902

Abstract: A cleaning material is applied to a surface of a substrate. The cleaning material includes one or more polymeric materials for entrapping contaminants present on the surface of the substrate. A rinsing fluid is applied to the surface of the substrate at a controlled velocity to effect removal of the cleaning material and contaminants entrapped within the cleaning material from the surface of the substrate. The controlled velocity of the rinsing fluid is set to cause the cleaning material to behave in an elastic manner when impacted by the rinsing fluid, thereby improving contaminant removal from the surface of the substrate.

Abstract translation: 将清洁材料施加到基板的表面。 清洁材料包括用于捕获存在于基底表面上的污染物的一种或多种聚合材料。 冲洗流体以受控的速度施加到基底的表面，以从衬底的表面去除被清除材料和被污染的清洁材料中的污染物。 洗涤流体的受控速度被设定为使得清洁材料在被冲洗流体冲击时以弹性方式表现，从而改善从基材表面去除污染物质。

公开(公告)号：US08483227B2

公开(公告)日：2013-07-09

申请号：US10718302

申请日：2003-11-20

Applicant: Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

Inventor： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC: H04L12/56

CPC classification number: H04L41/0896

Abstract: Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

Abstract translation: 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US20120125375A1

公开(公告)日：2012-05-24

申请号：US13115649

申请日：2011-05-25

Applicant: Ji Zhu ,  Arjun Mendiratta ,  David Mui

Inventor： Ji Zhu ,  Arjun Mendiratta ,  David Mui

IPC: B08B3/08 ,  B08B3/02 ,  B08B3/00

CPC classification number: C11D7/5009 ,  C11D3/3723 ,  C11D3/3765 ,  C11D3/3773 ,  C11D7/261 ,  C11D7/3263 ,  C11D7/34 ,  C11D11/0047 ,  H01L21/02057 ,  H01L21/67051 ,  Y10S134/902

Abstract: A cleaning material is applied to a surface of a substrate. The cleaning material includes one or more polymeric materials for entrapping contaminants present on the surface of the substrate. A rinsing fluid is applied to the surface of the substrate at a controlled velocity to effect removal of the cleaning material and contaminants entrapped within the cleaning material from the surface of the substrate. The controlled velocity of the rinsing fluid is set to cause the cleaning material to behave in an elastic manner when impacted by the rinsing fluid, thereby improving contaminant removal from the surface of the substrate.

Abstract translation: 将清洁材料施加到基板的表面。 清洁材料包括用于捕获存在于基底表面上的污染物的一种或多种聚合材料。 冲洗流体以受控的速度施加到基底的表面，以从衬底的表面去除被清除材料和被污染的清洁材料中的污染物。 洗涤流体的受控速度被设定为使得清洁材料在被冲洗流体冲击时以弹性方式表现，从而改善从基材表面去除污染物质。

公开(公告)号：US08105997B2

公开(公告)日：2012-01-31

申请号：US12267362

申请日：2008-11-07

Applicant: Ji Zhu ,  Arjun Mendiratta ,  David Mui

Inventor： Ji Zhu ,  Arjun Mendiratta ,  David Mui

IPC: C11D3/37

CPC classification number: B08B3/02 ,  C11D3/2079 ,  C11D3/222 ,  C11D3/37 ,  C11D3/3707 ,  C11D3/3723 ,  C11D3/3753 ,  C11D3/3765 ,  C11D3/3773 ,  C11D3/378 ,  C11D3/43 ,  C11D7/265 ,  C11D7/268 ,  C11D7/5004 ,  C11D11/0047 ,  C11D17/0013 ,  C11D17/003 ,  Y10S134/902

Abstract: The embodiments provide substrate cleaning techniques to remove contaminants from the substrate surface to improve device yield. The substrate cleaning techniques utilize a cleaning material with solid components and polymers with a large molecular weight dispersed in a cleaning liquid to form the cleaning material, which is fluidic. The solid components remove contaminants on the substrate surface by making contact with the contaminants. The polymers with large molecular weight form polymer chains and a polymeric network that capture and entrap solids in the cleaning materials, which prevent solids from falling on the substrate surface. In addition, the polymers can also assist in removing contaminants form the substrate surface by making contacts with contaminants on the substrate surface. In one embodiment, the cleaning material glides around protruding features on the substrate surface without making a forceful impact on the protruding features to damage them. The present invention can be implemented in numerous ways, including a material (or solution), a method, a process, an apparatus, or a system.

Abstract translation: 这些实施例提供了从衬底表面去除污染物以提高器件产量的衬底清洁技术。 基板清洗技术利用具有固体组分的清洁材料和分散在清洁液体中的大分子量聚合物以形成流体性的清洁材料。 固体组分通过与污染物接触来去除衬底表面上的污染物。 具有大分子量的聚合物形成聚合物链和聚合物网络，其捕获并捕获清洁材料中的固体，从而防止固体落在基材表面上。 此外，聚合物还可以通过与衬底表面上的污染物接触来帮助从衬底表面去除污染物。 在一个实施例中，清洁材料围绕衬底表面上的突出特征滑动，而不会对突出特征造成有力的影响以损坏它们。 本发明可以以多种方式实现，包括材料（或解决方案），方法，过程，装置或系统。