公开(公告)号：US06531324B2

公开(公告)日：2003-03-11

申请号：US09820039

申请日：2001-03-28

Applicant: Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

Inventor： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC: H01L2100

CPC classification number: H01L29/516 ,  H01L21/28291 ,  H01L29/78391

Abstract: A ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls is provided. The passivation sidewalls serve as an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

公开(公告)号：US06495378B2

公开(公告)日：2002-12-17

申请号：US09814273

申请日：2001-03-21

Applicant: Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

Inventor： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC: H01L2100

CPC classification number: H01L21/02197 ,  C23C16/40 ,  H01L21/02271 ,  H01L21/31604 ,  H01L21/31691

Abstract: A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.

Abstract translation: 提供Pb3GeO5相PGO薄膜。 该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。 该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。 该方法将Pd和锗在溶剂中混合。 将溶液加热以形成分解的前体蒸汽。 该方法提供沉积温度和压力。 沉积的膜也被退火以增强膜的铁弹性特征。 还提供了由本发明PGO膜制成的铁弹性电容器。

公开(公告)号：US06468901B1

公开(公告)日：2002-10-22

申请号：US09847873

申请日：2001-05-02

Applicant: Jer-shen Maa ,  Yoshi Ono ,  Fengyan Zhang

Inventor： Jer-shen Maa ,  Yoshi Ono ,  Fengyan Zhang

IPC: H01L2144

CPC classification number: H01L21/28518

Abstract: An integrated circuit device, and a method of manufacturing the same, including nickel silicide on a silicon substrate fabricated with an iridium interlayer. In one embodiment the method comprises depositing an iridium (Ir) interface layer between the Ni and Si layers prior to the silicidation reaction. The thermal stability is much improved by adding the thin iridium layer. This is shown by the low junction leakage current of the ultra-shallow junction, and by the low sheet resistance of the silicide, even after annealing at 850° C.

Abstract translation: 一种集成电路器件及其制造方法，包括用铱中间层制造的硅衬底上的硅化镍。 在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积铱（Ir）界面层。 通过添加薄铱层，热稳定性大大提高。 即使在850℃退火之后，超浅结的低结漏电流和硅化物的薄片电阻也被示出。

公开(公告)号：US06190963B1

公开(公告)日：2001-02-20

申请号：US09316661

申请日：1999-05-21

Applicant: Fengyan Zhang ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Wei-Wei Zhuang

Inventor： Fengyan Zhang ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Wei-Wei Zhuang

IPC: H01L218242

CPC classification number: H01L28/75 ,  H01L21/28568 ,  H01L28/55

Abstract: An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. A method for forming an Ir—M—O composite film barrier layer and an Ir—M—O composite film ferroelectric electrode are also provided.

Abstract translation: 已经提供了可用于形成铁电电容器的电极的Ir-M-O复合膜，其中M包括各种难熔金属。 Ir组合膜在氧气环境中耐高温退火。 当与由相同种类的M过渡金属制成的底层阻挡层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。 结果，不形成铱硅化物产物，这降低了电极界面的特性。 也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 Ir-M-O导电电极/屏障结构可用于非易失性FeRAM器件，DRAM，电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件。 还提供了形成Ir-M-O复合膜阻挡层和Ir-M-O复合膜铁电电极的方法。

公开(公告)号：US06190925B1

公开(公告)日：2001-02-20

申请号：US09302272

申请日：1999-04-28

Applicant: Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

Inventor： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC: H01L2100

CPC classification number: H01L21/31604 ,  C23C16/40 ,  H01L21/31691 ,  Y10S438/933

Abstract: The present invention provides a substantially single crystal PGO film with optimal the ferroelectric properties. The PGO film and adjacent electrodes are epitaxially grown to minimize mismatch between the structures. MOCVD deposition methods and RTP annealing procedures permit a PGO film to be epitaxially grown in commercial fabrication processes. These epitaxial ferroelectric have application in FeRAM memory devices. The present invention deposition method epitaxially grows ferroelectric Pb5Ge3O11 thin films along with c-axis orientation.

Abstract translation: 本发明提供了具有最佳铁电性能的基本单晶PGO膜。 PGO膜和相邻电极被外延生长以最小化结构之间的失配。 MOCVD沉积方法和RTP退火程序允许PGO膜在商业制造工艺中外延生长。 这些外延铁电体已经应用于FeRAM存储器件中。 本发明沉积方法外延生长铁电Pb5Ge3O11薄膜以及c轴取向。

公开(公告)号：US08242482B2

公开(公告)日：2012-08-14

申请号：US12042983

申请日：2008-03-05

Applicant: Sheng Teng Hsu ,  Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff

Inventor： Sheng Teng Hsu ,  Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff

IPC: H01L31/072

CPC classification number: H05B33/145

Abstract: An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

Abstract translation: 提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。 该方法包括：用纳米尖端形成底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。 纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。 通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。 在一个方面，Si磷光体层是SRSO层。 响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

公开(公告)号：US20080197399A1

公开(公告)日：2008-08-21

申请号：US11707712

申请日：2007-02-16

Applicant: Sheng Teng Hsu ,  Fengyan Zhang

Inventor： Sheng Teng Hsu ,  Fengyan Zhang

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L29/94 ,  B82Y10/00 ,  H01L28/91 ,  H01L29/66083

Abstract: A nanotip capacitor and associated fabrication method are provided. The method provides a bottom electrode and grows electrically conductive nanotips overlying the bottom electrode. An electrically insulating dielectric is deposited overlying the nanotips, and an electrically conductive top electrode is deposited overlying dielectric-covered nanotips. Typically, the dielectric is deposited by forming a thin layer of dielectric overlying the nanotips using an atomic layer deposition (ALD) process. In one aspect, the electrically insulating dielectric covering the nanotips forms a three-dimensional interface of dielectric-covered nanotips. Then, the electrically conductive top electrode overlying the dielectric-covered nanotips forms a three-dimensional top electrode interface, matching the first three-dimensional interface of the dielectric-covered nanotips.

Abstract translation: 提供了一种纳米尖端电容器和相关联的制造方法。 该方法提供底部电极并且生长覆盖底部电极的导电的纳米技术。 沉积覆盖在纳米尖端上的电绝缘电介质，并且将导电顶部电极沉积在覆盖有电介质的纳米尖端上。 通常，通过使用原子层沉积（ALD）工艺形成覆盖在纳米尖端上的介电层的薄层来沉积电介质。 在一个方面，覆盖纳米尖端的电绝缘电介质形成介电覆盖的纳米尖端的三维界面。 然后，覆盖介电覆盖的纳米尖端的导电顶部电极形成三维顶部电极接口，与介电覆盖的纳米尖端的第一个三维界面相匹配。

公开(公告)号：US20080096345A1

公开(公告)日：2008-04-24

申请号：US11580623

申请日：2006-10-12

Applicant: Fengyan Zhang ,  David R. Evans ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  David R. Evans ,  Sheng Teng Hsu

IPC: H01G9/00 ,  H01L21/8242

CPC classification number: H01G9/07 ,  Y10S977/762 ,  Y10T29/417

Abstract: A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface. A top electrode is formed overlying the nanowire shells. A main cavity is formed between the top electrode and bottom electrodes, partially displaced by a first plurality of nanowire shells. Electrolyte cavities are formed between the sleeves and nanowires by etching the first sacrificial layer. In one aspect, electrolyte cavities are formed between the bottom electrode top surface and a shell coating layer joining the sleeve bottom openings. Then, the main and electrolyte cavities are filled with either a liquid or gas phase electrolyte. In a different aspect, the first sacrificial layer is a solid phase electrolyte that is not etched away.

Abstract translation: 提供了形成纳米电化学（NEC）电池的方法。 该方法提供了具有顶部表面的底部电极。 形成纳米线贝壳。 每个纳米线壳具有纳米线和套管，纳米线连接到底部电极顶表面。 顶部电极形成在纳米线壳上。 在顶部电极和底部电极之间形成主要腔室，部分地被第一多个纳米线壳体置换。 通过蚀刻第一牺牲层，在套筒和纳米线之间形成电解质空腔。 在一个方面，在底部电极顶表面和连接套筒底部开口的外壳涂层之间形成电解质腔。 然后，主要和电解质空腔填充有液相或气相电解质。 在不同的方面，第一牺牲层是不被蚀刻掉的固相电解质。

公开(公告)号：US20080092955A1

公开(公告)日：2008-04-24

申请号：US11582197

申请日：2006-10-16

Applicant: Fengyan Zhang ,  Robert A. Barrowcliff ,  Gregory M. Stecker ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Robert A. Barrowcliff ,  Gregory M. Stecker ,  Sheng Teng Hsu

IPC: H01L31/00

CPC classification number: H01G9/2031 ,  H01G9/2059 ,  H01L51/0036 ,  H01L51/0086 ,  H01L51/4226 ,  Y02E10/542

Abstract: A method of fabricating a photovoltaic cell for use in a solar cell structure includes preparing a first substrate; preparing a TiO2 precursor; preparing a cold wall CVD chamber; placing the first substrate in the cold wall CVD chamber; forming a transparent conducting electrode on the first substrate; depositing a porous column TiO2 film on the transparent conducting electrode; depositing a photosensitive material in and on the porous column TiO2 film; forming a top electrode on the photovoltaic cell; and incorporating the photovoltaic cell into a solar cell structure. The method of the invention is suitable for forming photovoltaic cells which may be of the dye-sensitized solar cell (DSSC) type, having a liquid or solid-state electrolyte therein, or an ordered organic-inorganic heterojunction photovoltaic cell.

Abstract translation: 制造太阳能电池结构中使用的太阳能电池的方法包括制备第一基板; 制备TiO 2前体; 准备冷壁CVD室; 将第一衬底放置在冷壁CVD室中; 在所述第一基板上形成透明导电电极; 在透明导电电极上沉积多孔柱TiO 2膜; 在多孔色谱柱TiO 2膜上沉积感光材料; 在所述光伏电池上形成顶部电极; 并将光伏电池并入太阳能电池结构中。 本发明的方法适用于形成可能是其中具有液体或固态电解质的染料敏化太阳能电池（DSSC）型或有序无机异质结光伏电池的光伏电池。

公开(公告)号：US20080010707A1

公开(公告)日：2008-01-10

申请号：US11264113

申请日：2005-11-01

Applicant: Fengyan Zhang ,  Robert Barrowcliff ,  Jong-Jan Lee ,  Sheng Hsu

Inventor： Fengyan Zhang ,  Robert Barrowcliff ,  Jong-Jan Lee ,  Sheng Hsu

IPC: C30B25/00 ,  C30B23/00 ,  C30B28/12

CPC classification number: B81C1/00182 ,  B81B2201/0214 ,  Y10S977/712 ,  Y10S977/762

Abstract: An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.

Abstract translation: 提供了一种周围环境纳米线传感器和相应的制造方法。 该方法包括：形成诸如硅（Si）或玻璃的衬底; 生长纳米线 沉积覆盖在纳米线上的绝缘体层; 蚀刻以暴露纳米线的尖端; 形成图案化的金属电极，其边缘覆盖在纳米线的尖端上; 并且蚀刻以暴露电极边缘下方的纳米线。 纳米线可以是诸如IrO 2，TiO 2，InO，ZnO，SnO 2，Sb 2，N 2的材料 例如，在实施例3中，可以举出例如“O 3”，“3”，“ 绝缘体层可以是旋涂玻璃（SOG）或低k电介质。 一方面，所得结构包括从掺杂衬底区域生长的暴露的纳米线和具有嵌入的纳米线的绝缘体芯。 在不同的方面，该方法形成覆盖衬底的生长促进层。 所得结构包括从选择性形成的生长促进层生长的暴露的纳米线。