公开(公告)号：US06720258B2

公开(公告)日：2004-04-13

申请号：US10319313

申请日：2002-12-12

申请人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L2144

CPC分类号： H01L21/28518 ,  H01L29/456

摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

摘要翻译： 集成电路器件及其制造方法包括在（100）Si上的外延硅化镍，或者由钴中间层制造的在非晶Si上的稳定的硅化镍。 在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积钴（Co）界面层。 钴中间层通过由钴中间层与镍和硅的反应形成的钴/镍/硅合金层调节Ni原子的通量，使得Ni原子以相似的速率到达Si界面，即没有 任何取向偏好，从而形成均匀的硅化镍层。 可以将镍硅化物退火以形成均匀的结晶二硅化镍。 因此，实现了（100）Si或非晶Si上的单晶硅化镍，其中硅化镍具有改进的稳定性并可用于超浅结结器件中。

公开(公告)号：US06468901B1

公开(公告)日：2002-10-22

申请号：US09847873

申请日：2001-05-02

申请人： Jer-shen Maa ,  Yoshi Ono ,  Fengyan Zhang

发明人： Jer-shen Maa ,  Yoshi Ono ,  Fengyan Zhang

IPC分类号： H01L2144

CPC分类号： H01L21/28518

摘要： An integrated circuit device, and a method of manufacturing the same, including nickel silicide on a silicon substrate fabricated with an iridium interlayer. In one embodiment the method comprises depositing an iridium (Ir) interface layer between the Ni and Si layers prior to the silicidation reaction. The thermal stability is much improved by adding the thin iridium layer. This is shown by the low junction leakage current of the ultra-shallow junction, and by the low sheet resistance of the silicide, even after annealing at 850° C.

摘要翻译： 一种集成电路器件及其制造方法，包括用铱中间层制造的硅衬底上的硅化镍。 在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积铱（Ir）界面层。 通过添加薄铱层，热稳定性大大提高。 即使在850℃退火之后，超浅结的低结漏电流和硅化物的薄片电阻也被示出。

公开(公告)号：US06534871B2

公开(公告)日：2003-03-18

申请号：US09855391

申请日：2001-05-14

申请人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L2348

CPC分类号： H01L21/28518 ,  H01L29/456

摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

公开(公告)号：US07267996B2

公开(公告)日：2007-09-11

申请号：US10923165

申请日：2004-08-20

申请人： Fengyan Zhang ,  David R. Evans ,  Wei Pan ,  Lisa H. Stecker ,  Jer-Shen Maa

发明人： Fengyan Zhang ,  David R. Evans ,  Wei Pan ,  Lisa H. Stecker ,  Jer-Shen Maa

IPC分类号： H01L21/467

CPC分类号： H01L21/32136 ,  H01L21/28291

摘要： A method of etching an iridium layer for use in a ferroelectric device includes preparing a substrate; depositing a barrier layer on the substrate; depositing an iridium layer on the barrier layer; depositing a hard mask layer on the iridium layer; depositing, patterning and developing a photoresist layer on the hard mask; etching the hard mask layer; etching the iridium layer using argon, oxygen and chlorine chemistry in a high-density plasma reactor; and completing the ferroelectric device.

摘要翻译： 蚀刻用于铁电体器件的铱层的方法包括：制备衬底; 在衬底上沉积阻挡层; 在阻挡层上沉积铱层; 在铱层上沉积硬掩模层; 在硬掩模上沉积，图案化和显影光致抗蚀剂层; 蚀刻硬掩模层; 在高密度等离子体反应器中使用氩，氧和氯化学蚀刻铱层; 并完成铁电器件。

公开(公告)号：US20060040493A1

公开(公告)日：2006-02-23

申请号：US10923165

申请日：2004-08-20

申请人： Fengyan Zhang ,  David Evans ,  Wei Pan ,  Lisa Stecker ,  Jer-Shen Maa

发明人： Fengyan Zhang ,  David Evans ,  Wei Pan ,  Lisa Stecker ,  Jer-Shen Maa

IPC分类号： H01L21/44

CPC分类号： H01L21/32136 ,  H01L21/28291

摘要： A method of etching an iridium layer for use in a ferroelectric device includes preparing a substrate; depositing a barrier layer on the substrate; depositing an iridium layer on the barrier layer; depositing a hard mask layer on the iridium layer; depositing, patterning and developing a photoresist layer on the hard mask; etching the hard mask layer; etching the iridium layer using argon, oxygen and chlorine chemistry in a high-density plasma reactor; and completing the ferroelectric device.

摘要翻译： 蚀刻用于铁电体器件的铱层的方法包括：制备衬底; 在衬底上沉积阻挡层; 在阻挡层上沉积铱层; 在铱层上沉积硬掩模层; 在硬掩模上沉积，图案化和显影光致抗蚀剂层; 蚀刻硬掩模层; 在高密度等离子体反应器中使用氩，氧和氯化学蚀刻铱层; 并完成铁电器件。

公开(公告)号：US06682995B2

公开(公告)日：2004-01-27

申请号：US10317742

申请日：2002-12-11

申请人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L213205

CPC分类号： H01L29/456 ,  H01L21/28291 ,  H01L28/55 ,  H01L28/65

摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

摘要翻译： 已经提供了具有高温稳定性的导电阻挡层，其可用作铁电电容器电极。 该导电屏障允许在涉及退火的IC工艺中使用铱（Ir）金属。 已经发现，分离硅衬底与Ir膜与中间相邻的钽（Ta）膜非常有效地抑制层之间的扩散。 Ir防止退火过程中氧进入硅的相互扩散。 Ta或TaN层防止Ir扩散到硅中。 这种Ir / TaN结构保护了硅界面，从而使粘附，电导，小丘和剥离问题最小化。 使用覆盖Ir / TaN结构的Ti也有助于防止退火过程中的小丘形成。 还提供了形成多层Ir导电结构和Ir铁电电极的方法。

公开(公告)号：US06190963B1

公开(公告)日：2001-02-20

申请号：US09316661

申请日：1999-05-21

申请人： Fengyan Zhang ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Wei-Wei Zhuang

发明人： Fengyan Zhang ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Wei-Wei Zhuang

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L28/55

摘要： An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. A method for forming an Ir—M—O composite film barrier layer and an Ir—M—O composite film ferroelectric electrode are also provided.

摘要翻译： 已经提供了可用于形成铁电电容器的电极的Ir-M-O复合膜，其中M包括各种难熔金属。 Ir组合膜在氧气环境中耐高温退火。 当与由相同种类的M过渡金属制成的底层阻挡层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。 结果，不形成铱硅化物产物，这降低了电极界面的特性。 也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 Ir-M-O导电电极/屏障结构可用于非易失性FeRAM器件，DRAM，电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件。 还提供了形成Ir-M-O复合膜阻挡层和Ir-M-O复合膜铁电电极的方法。

公开(公告)号：US06537361B2

公开(公告)日：2003-03-25

申请号：US09822637

申请日：2001-03-30

申请人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L2122

CPC分类号： H01L21/02197 ,  C01G21/00 ,  C01P2002/86 ,  H01L21/02112 ,  H01L21/02175 ,  H01L21/02282 ,  H01L21/31604 ,  H01L21/31691

摘要： A method of synthesizing a PGO spin-coating precursor solution includes utilizing the starting materials of lead acetate trihydrate (Pb(OAc)2•3H2O) and germanium alkoxide (Ge(OR)4(R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol) ethyl ether. The mixed solution of lead and di(ethylene glycol) ethyl ether is heated in an atmosphere of air at a temperature no greater than 185° C., and preferably no greater than 190° C. for a time period in a range of thirty minutes to four hours. During the heating step the color of the solution is monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol) ethyl ether to make the PGO spin-coating solution. This second step also entails heating the solution to a temperature no greater than 190° C. for a time period in a range of 0.5 to 2.0 hours. The process results in a PGO precursor solution suitable for use in spin-coating.

公开(公告)号：US06555456B2

公开(公告)日：2003-04-29

申请号：US10037192

申请日：2001-11-09

申请人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L213205

CPC分类号： H01L29/456 ,  H01L21/28291 ,  H01L28/55 ,  H01L28/65

摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

公开(公告)号：US06541385B2

公开(公告)日：2003-04-01

申请号：US09855393

申请日：2001-05-14

申请人： Hong Ying ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Hong Ying ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21302

CPC分类号： H01L21/02071 ,  C04B41/009 ,  C04B41/5346 ,  C04B41/91 ,  C04B2111/00844 ,  H01L21/32136 ,  H01L28/60 ,  C04B35/495

摘要： A method of forming an electrode in an integrated circuit includes preparing a silicon-base substrate, including forming semiconductor structures on the substrate to form an integrated substrate structure; depositing a layer of electrode material on a substrate structure; patterning the layer of electrode material to form electrode elements, wherein said patterning includes plasma etching the layer of electrode material in a plasma reactor in an etching gas atmosphere having a fluorine component therein; and cleaning the substrate structure and electrode elements in a distilled water bath.