公开(公告)号：US08652891B1

公开(公告)日：2014-02-18

申请号：US13812867

申请日：2012-08-27

Applicant: Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L21/338

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

Abstract: The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced.

Abstract translation: 本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 沿着第一方向位于所述多个源区和漏区之间的多个沟道区; 其特征在于，所述多个栅极堆叠结构包围所述多个沟道区域。 根据本发明的半导体器件及其制造方法，通过使用组合来对通道区域所在的鳍进行冲压和蚀刻来形成全自动纳米线金属多栅极的自对准 的硬掩模和伪栅极，从而提高了器件性能。

公开(公告)号：US20130316509A1

公开(公告)日：2013-11-28

申请号：US13580962

申请日：2012-06-12

Applicant: Changliang Qin ,  Huaxiang Yin

Inventor： Changliang Qin ,  Huaxiang Yin

IPC: H01L21/336

CPC classification number: H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: The present invention provides a manufacturing method for a semiconductor device having epitaxial source/drain regions, in which a diffusion barrier layer of the source/drain regions made of epitaxial silicon-carbon or germanium silicon-carbon are added on the basis of epitaxially growing germanium-silicon of the source/drain regions in the prior art process, and the introduction of the diffusion barrier layer of the source/drain regions prevents diffusion of the dopant in the source/drain regions, thus mitigating the SCE and DIBL effect. The use of the diffusion barrier layer for the source/drain regions can also reduce the dosage of HALO implantation in the subsequent step, thus if HALO is performed before epitaxial growth of the source/drain regions, impact on the surfaces of the source/drain regions can be alleviated; if HALO is performed after epitaxial growth of the source/drain regions, the stress release effect of the epitaxial layer of the source drain/regions caused by the implantation can be reduced as much as possible.

Abstract translation: 本发明提供了一种具有外延源极/漏极区域的半导体器件的制造方法，其中基于外延生长锗添加由外延硅 - 碳或锗硅 - 碳制成的源极/漏极区的扩散阻挡层 在现有技术的工艺中源极/漏极区域的硅，以及源极/漏极区域的扩散阻挡层的引入防止了掺杂剂在源/漏区域中的扩散，从而减轻了SCE和DIBL效应。 用于源极/漏极区域的扩散阻挡层的使用也可以降低后续步骤中的HALO注入的剂量，因此如果在源极/漏极区域的外延生长之前执行HALO，则冲击源极/漏极 地区可以缓解; 如果在源/漏区的外延生长之后执行HALO，则可以尽可能地减少由注入引起的源漏极/区域的外延层的应力释放效应。

公开(公告)号：US20130256808A1

公开(公告)日：2013-10-03

申请号：US13520791

申请日：2012-04-11

Applicant: Huaxiang Yin ,  xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L27/088 ,  H01L21/8236

CPC classification number: H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

Abstract: The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.

Abstract translation: 本发明公开了一种半导体器件，包括第一MOSFET; 第二个MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力衬垫; 覆盖所述第二MOSFET并具有第二应力的第二应力衬垫; 其中所述第二应力衬垫和/或所述第一应力衬垫包括金属氧化物。 根据本发明的高应力CMOS及其制造方法，通过使用CMOS兼容工艺，分别在PMOS和NMOS上选择性地形成包含金属氧化物的应力层，由此，沟道区域的载流子迁移率有效地 增强了设备的性能，提高了设备​​性能。

公开(公告)号：US20130256664A1

公开(公告)日：2013-10-03

申请号：US13519884

申请日：2012-04-10

Applicant: Changliang Qin ,  Huaxiang Yin

Inventor： Changliang Qin ,  Huaxiang Yin

IPC: H01L29/10 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first spacer, such that the substrate material below the amorphous material layer is exposed to the solution and is etched thereby, and in the end, forming a Sigma shaped recess that extends to the nearby region below the gate stack; and epitaxially forming SiGe in the Sigma shaped recess.

Abstract translation: 本发明涉及一种用于使源极/漏极区域更靠近沟道区域的MOS器件及其制造方法，包括：提供包括衬底，有源区域和栅极堆叠的初始结构; 在栅极堆叠的两侧上的有源区中进行离子注入，使得衬底材料的一部分经历预非晶化以形成无定形材料层; 形成第一间隔物; 以第一间隔物作为掩模，进行干蚀刻，从而形成凹部，保持第一间隔物下面的非晶材料层; 使用对非晶材料层各向同性的蚀刻剂溶液进行湿蚀刻，并且其对非晶材料层的蚀刻速率大于或基本上等于对基板材料的{100}和{110}表面的蚀刻速率，但是 远远大于衬底材料的{111}表面的蚀刻速率，从而去除第一间隔物下方的无定形材料层，使得无定形材料层下面的衬底材料暴露于溶液并被蚀刻，并且在 结束，形成延伸到栅堆叠下方的附近区域的Sigma形凹部; 并在Sigma形凹部中外延形成SiGe。

公开(公告)号：US08508009B2

公开(公告)日：2013-08-13

申请号：US12662607

申请日：2010-04-26

Applicant: Huaxiang Yin ,  Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

Inventor： Huaxiang Yin ,  Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

IPC: H01L31/062 ,  H01L27/146 ,  H01L31/107

CPC classification number: H01L27/14627 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02327

Abstract: A microlens, an image sensor including the microlens, a method of forming the microlens and a method of manufacturing the image sensor are provided. The microlens includes a polysilicon pattern, having a cylindrical shape, formed on a substrate, and a round-type shell portion enclosing the polysilicon pattern. The microlens may further include a filler material filling an interior of the shell portion, or a second shell portion covering the first shell portion. The method of forming a microlens includes forming a silicon pattern on a semiconductor substrate having a lower structure, forming a capping film on the semiconductor substrate over the silicon pattern, annealing the silicon pattern and the capping film altering the silicon pattern to a polysilicon pattern having a cylindrical shape and the capping film to a shell portion for a round-type microlens, and filling an interior of the shell portion with a lens material through an opening between the semiconductor substrate and an edge of the shell portion. The image sensor includes a microlens formed by a similar method and a photodiode having a cylindrical shape.

Abstract translation: 提供微透镜，包括微透镜的图像传感器，形成微透镜的方法和制造图像传感器的方法。 微透镜包括形成在基板上的具有圆柱形状的多晶硅图案和包围多晶硅图案的圆形外壳部分。 微透镜还可以包括填充壳体部分的内部的填充材料或覆盖第一壳体部分的第二壳体部分。 形成微透镜的方法包括在具有较低结构的半导体衬底上形成硅图案，在硅图案上的半导体衬底上形成覆盖膜，使硅图案和覆盖膜退火，将硅图案改变为具有 圆筒形，并且封盖膜用于圆形微透镜的外壳部分，并且通过半导体基板和外壳部分的边缘之间的开口用透镜材料填充外壳部分的内部。 图像传感器包括通过类似方法形成的微透镜和具有圆柱形状的光电二极管。

公开(公告)号：US20130040465A1

公开(公告)日：2013-02-14

申请号：US13381005

申请日：2011-08-10

Applicant: Lingkuan Meng ,  Huaxiang Yin

Inventor： Lingkuan Meng ,  Huaxiang Yin

IPC: H01L21/3065

CPC classification number: H01L21/31055 ,  H01L21/76801 ,  H01L29/78

Abstract: The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.

Abstract translation: 本发明公开了一种用于在层间电介质（ILD）的位置 - 接近界​​面处的平坦化的回蚀方法，包括：通过化学气相沉积或氧化方法在晶片的表面上沉积或生长厚SiO 2层; 旋涂一层SOG，然后进行热处理以获得相对均匀的堆叠结构; 使用等离子体蚀刻对SOG进行回蚀，并且在接近SiO 2的位置 - 接近界​​面时停止; 在靠近界面的位置处对剩余的SOG / SiO 2结构进行等离子体回蚀，直到达到期望的厚度。 由于在位置 - 接近界​​面处进行两步蚀刻，因此获得了非常好的ILD平滑表面。 也就是说，ILD的平面和整洁的表面不仅在中心区域中获得，而且在晶片的边缘处获得。

公开(公告)号：US20130026496A1

公开(公告)日：2013-01-31

申请号：US13496198

申请日：2011-11-28

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L29/16 ,  H01L29/788 ,  H01L21/336

CPC classification number: H01L29/66833 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for manufacturing a semiconductor device, comprising forming a tunneling dielectric layer, a storage dielectric layer, a gate dielectric layer and a gate layer sequentially on a semiconductor substrate of a first semiconductor material; patterning the tunneling dielectric layer, the storage dielectric layer, the gate dielectric layer and the gate layer to form a gate stack; forming a groove in the semiconductor substrate on the sides of the gate stack; filling the groove with a second semiconductor material different from the first semiconductor material, meanwhile, the entire device is covered by the dielectric layer. The surface energy level in the channel is made to change by the stress generated by the second semiconductor material and the covering dielectric layer, thereby increasing tunneling current and improving the storage efficiency of the device.

Abstract translation: 一种制造半导体器件的方法，包括在第一半导体材料的半导体衬底上依次形成隧道电介质层，存储电介质层，栅极电介质层和栅极层; 图案化隧道介电层，存储介质层，栅极介电层和栅极层以形成栅极堆叠; 在所述半导体衬底的所述栅堆叠的侧面上形成沟槽; 用不同于第一半导体材料的第二半导体材料填充凹槽，同时整个器件被电介质层覆盖。 通过由第二半导体材料和覆盖介电层产生的应力来改变通道中的表面能级，从而增加隧道电流并提高器件的存储效率。

公开(公告)号：US20120181634A1

公开(公告)日：2012-07-19

申请号：US13318344

申请日：2011-04-20

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

Abstract: The present invention relates to a method of introducing strain into a channel and a device manufactured by using the method, the method comprising: providing a semiconductor substrate; forming a channel in the semiconductor substrate; forming a first gate dielectric layer on the channel; forming a polysilicon gate layer on the first gate dielectric layer; doping or implanting a first element into the polysilicon gate layer; removing a part of the first gate dielectric layer and polysilicon gate layer to thereby form a first gate structure; forming a source/drain extension region in the channel; forming spacers on both sides of the first gate structure; forming a source/drain in the channel; and performing annealing such that lattice change occurs in the polysilicon that is doped or implanted with the first element in the high-temperature crystallization process, thereby producing a first strain in the polysilicon gate layer, and introducing the first strain through the gate dielectric layer to the channel. This method has greater process flexibility and simple process complexity with no additional process cost.

Abstract translation: 本发明涉及将应变引入通道的方法和使用该方法制造的器件，该方法包括：提供半导体衬底; 在半导体衬底中形成通道; 在所述通道上形成第一栅介质层; 在所述第一栅极介电层上形成多晶硅栅极层; 将第一元件掺杂或注入到多晶硅栅极层中; 去除所述第一栅极介电层和多晶硅栅极层的一部分，从而形成第一栅极结构; 在通道中形成源极/漏极延伸区域; 在第一栅极结构的两侧形成间隔物; 在通道中形成源极/漏极; 并且进行退火，使得在高温结晶工艺中掺杂或注入第一元素的多晶硅中发生晶格变化，从而在多晶硅栅极层中产生第一应变，并将第一应变通过栅极介电层引入到 这个频道。 该方法具有更大的工艺灵活性和简单的工艺复杂性，无需额外的工艺成本。

公开(公告)号：US08187905B2

公开(公告)日：2012-05-29

申请号：US12805821

申请日：2010-08-20

Applicant: Huaxiang Yin ,  Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

Inventor： Huaxiang Yin ,  Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

IPC: H01L31/062 ,  H01L31/107

CPC classification number: H01L27/14627 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02327

Abstract: A microlens, an image sensor including the microlens, a method of forming the microlens and a method of manufacturing the image sensor are provided. The microlens includes a polysilicon pattern, having a cylindrical shape, formed on a substrate, and a round-type shell portion enclosing the polysilicon pattern. The microlens may further include a filler material filling an interior of the shell portion, or a second shell portion covering the first shell portion. The method of forming a microlens includes forming a silicon pattern on a semiconductor substrate having a lower structure, forming a capping film on the semiconductor substrate over the silicon pattern, annealing the silicon pattern and the capping film altering the silicon pattern to a polysilicon pattern having a cylindrical shape and the capping film to a shell portion for a round-type microlens, and filling an interior of the shell portion with a lens material through an opening between the semiconductor substrate and an edge of the shell portion. The image sensor includes a microlens formed by a similar method and a photodiode having a cylindrical shape.

Abstract translation: 提供微透镜，包括微透镜的图像传感器，形成微透镜的方法和制造图像传感器的方法。 微透镜包括形成在基板上的具有圆柱形状的多晶硅图案和包围多晶硅图案的圆形外壳部分。 微透镜还可以包括填充壳体部分的内部的填充材料或覆盖第一壳体部分的第二壳体部分。 形成微透镜的方法包括在具有较低结构的半导体衬底上形成硅图案，在硅图案上的半导体衬底上形成覆盖膜，使硅图案和覆盖膜退火，将硅图案改变为具有 圆筒形，并且封盖膜用于圆形微透镜的外壳部分，并且通过半导体基板和外壳部分的边缘之间的开口用透镜材料填充外壳部分的内部。 图像传感器包括通过类似方法形成的微透镜和具有圆柱形状的光电二极管。

公开(公告)号：US20110230021A1

公开(公告)日：2011-09-22

申请号：US13067306

申请日：2011-05-24

Applicant: Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

Inventor： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L27/0922 ,  H01L27/1225 ,  H01L27/1251

Abstract: Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.