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    Nonvolatile semiconductor memory with a programming operation and the method thereof
    62.
    发明申请
    Nonvolatile semiconductor memory with a programming operation and the method thereof 有权
    具有编程操作的非易失性半导体存储器及其方法

    公开(公告)号：US20050030790A1

    公开(公告)日：2005-02-10

    申请号：US10927716

    申请日：2004-08-27

    Applicant: Jae-Yong Jeong ,  Sung-Soo Lee

    Inventor： Jae-Yong Jeong ,  Sung-Soo Lee

    IPC: G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C11/34

    CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/10

    Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.

    Abstract translation: 本发明提供了一种在非易失性半导体存储器件中进行编程的方法，该方法具有连接到多个位线的多个存储单元串，并且由多个存储单元晶体管组成，多个存储单元晶体管的栅极耦合到多个字线， 与位线对应的寄存器。 所述方法包括将第一电压施加到位线中的第一位置，并将第二电压施加到所述位线中的第二位置，所述第一位线与所述第二位线相邻，所述第一和第二电压从所述寄存器提供; 将第一和第二位线与其对应的寄存器电隔离; 将第一位线充电至高于第一电压并低于第二电压的第三电压; 以及在将当前路径切断到所述第一和第二位线之后，将第四电压施加到字线。

    Nonvolatile semiconductor memory with a programming operation and the method thereof
    63.
    发明授权
    Nonvolatile semiconductor memory with a programming operation and the method thereof 有权

    公开(公告)号：US06650566B2

    公开(公告)日：2003-11-18

    申请号：US10021639

    申请日：2001-12-12

    Applicant: Jae-Yong Jeong ,  Sung-Soo Lee

    Inventor： Jae-Yong Jeong ,  Sung-Soo Lee

    IPC: G11C1604

    CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/10

    Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.

    Non-volatile memory, method of operating the same, memory system including the same, and method of operating the system
    64.
    发明授权
    Non-volatile memory, method of operating the same, memory system including the same, and method of operating the system 有权
    非易失性存储器，操作方法，包括相同的存储器系统以及操作系统的方法

    公开(公告)号：US08885409B2

    公开(公告)日：2014-11-11

    申请号：US13618604

    申请日：2012-09-14

    Applicant: Sang Hoon Lee ,  Hyun Seok Kim ,  Sung-Hwan Bae ,  Jong-Nam Baek ,  Jae Yong Jeong

    Inventor： Sang Hoon Lee ,  Hyun Seok Kim ,  Sung-Hwan Bae ,  Jong-Nam Baek ,  Jae Yong Jeong

    IPC: G11C16/04

    CPC classification number: G11C16/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/26 ,  G11C29/00

    Abstract: A nonvolatile memory device includes an array of nonvolatile memory cells and a plurality of page buffers configured to receive a plurality of pages of data read from the same page in the array using different read voltage conditions. A control circuit is provided, which is electrically coupled to the plurality of page buffers. The control circuit is configured to perform a test operation by driving the plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits, which are derived from a comparison of at least two of the multiple pages of data read from the same page of nonvolatile memory cells using the different read voltage conditions. An input/output device is provided, which is configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device.

    Abstract translation: 非易失性存储器件包括非易失性存储器单元的阵列和多个页缓冲器，其被配置为使用不同的读取电压条件从阵列中的同一页面接收多页数据。 提供了一种控制电路，其电耦合到多个页面缓冲器。 控制电路被配置为通过用控制信号驱动多个页面缓冲器来执行测试操作，该控制信号导致非易失性存储器件内的异或数据位串的产生，这是从多个页面中的至少两个的比较导出的 使用不同的读取电压条件从同一页的非易失性存储单元读取数据。 提供了一种输入/输出设备，其被配置为将从XOR数据位串导出的测试数据输出到位于非易失性存储器件外部的另一个设备。

    Method for computing maximum traffic capacitance of a base station using a virtual call
    66.
    再颁专利
    Method for computing maximum traffic capacitance of a base station using a virtual call 有权
    使用虚拟呼叫计算基站的最大流量电容的方法

    公开(公告)号：USRE43208E1

    公开(公告)日：2012-02-21

    申请号：US12504182

    申请日：2009-07-16

    Applicant: Seung Bong Yang ,  Jae Hwan Choi ,  Jae Yong Jeong

    Inventor： Seung Bong Yang ,  Jae Hwan Choi ,  Jae Yong Jeong

    IPC: H04W24/00

    CPC classification number: H04W24/00

    Abstract: A method for computing maximum traffic capacitance of a base station using a virtual call in the digital mobile communication system in such a way that an operator at operating terminal for Base Station Manager (BSM) inputs call-set-request instructions using the virtual call to maintain and repair the digital mobile communication system so that traffic state is set between mobile stations in the service area of test base station and a vocoder of a Base Station Controller (BSC) to compute maximum traffic capacitance of the test base station. An operator at operation terminal inputs call set information by operator instruction as much as mobile station numbers to be tested to compute maximum traffic capacitance of the base station. The BSM inputs a virtual call-set-request-instruction by means of a virtual call-set-start-flag. A virtual call-set-path is given among the vocoder of the BSC, the channel element, and the mobile station without going through Mobile Switching Center (MSC) that processes call setting and switching of a traffic path.

    Abstract translation: 一种用于在数字移动通信系统中使用虚拟呼叫计算基站的最大业务电容的方法，使得用于基站管理器（BSM）的操作终端的操作员使用虚拟呼叫输入呼叫组请求指令 维护和修复数字移动通信系统，使得在测试基站的服务区域中的移动站和基站控制器（BSC）的声码器之间设置业务状态，以计算测试基站的最大业务量。 操作终端的操作员通过操作员指令输入呼叫集信息，以及要测试的移动台号码，以计算基站的最大业务电容。 BSM通过虚拟呼叫设置开始标志输入虚拟呼叫设置请求指令。 在BSC的声码器，信道单元和移动站之间给出虚拟呼叫路径，而不经过处理呼叫设置和交换路径的移动交换中心（MSC）。

    Flash memory devices and programming methods that vary programming conditions in response to a selected step increment
    68.
    发明授权
    Flash memory devices and programming methods that vary programming conditions in response to a selected step increment 有权
    闪存器件和编程方法可以响应于选定的步进增量而改变编程条件

    公开(公告)号：US07787305B2

    公开(公告)日：2010-08-31

    申请号：US12134648

    申请日：2008-06-06

    Applicant: In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

    Inventor： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

    IPC: G11C16/04

    CPC classification number: G11C16/10

    Abstract: A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.

    Abstract translation: 一种闪速存储器件包括：闪存单元阵列，具有布置有字线和位线的闪速存储器单元;字线驱动器电路，被配置为在编程操作期间以选定的阶跃增量驱动所述字线，所述体电压电源电路被配置为 将大容量电压提供到闪存单元阵列的大部分中;以及写入电路，其被配置为驱动在编程操作期间由条件选择的位线。 控制逻辑块被配置为在编程操作期间控制写入电路和体电压电源电路。 控制逻辑块被配置为使得写入电路和/或体电压电源电路响应于所选择的步进增量来改变写入电路和/或体电压的条件中的至少一个。

    Non-volatile memory device and method capable of re-verifying a verified memory cell
    69.
    发明授权
    Non-volatile memory device and method capable of re-verifying a verified memory cell 有权
    能够重新验证经过验证的存储单元的非易失性存储器件和方法

    公开(公告)号：US07474566B2

    公开(公告)日：2009-01-06

    申请号：US11763606

    申请日：2007-06-15

    Applicant: Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

    Inventor： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

    IPC: G11C16/06

    CPC classification number: G11C16/3454

    Abstract: A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification data buffer, and re-verifying the memory cells by repeating the programming and verifying operations at least once with respect to the memory cells that were successfully verified, based on the verification result written to the verification data buffer. A non-volatile memory device includes a program data buffer storing first data, a verification data buffer copying and storing the first data, a plurality of memory cells programmed based on the data stored in the verification data buffer, a comparator comparing data stored in the verification data buffer with data read out from the programmed memory cells and outputting comparison data generated based on a result of the comparison to the verification data buffer, and a control unit controlling the program data buffer, the verification data buffer, the memory cells, and the comparator to additionally program or verify the memory cells that were successfully verified, based on the first data.

    Abstract translation: 驱动非易失性存储器件的方法包括：基于从程序数据缓冲器复制到验证数据缓冲器的第一数据来编程多个存储器单元，通过覆盖编程的存储器单元的验证结果来验证存储器单元 并且基于写入验证数据缓冲器的验证结果，通过重复对相对于成功验证的存储器单元的编程和验证操作至少一次来重新验证存储器单元。 非易失性存储装置包括存储第一数据的程序数据缓冲器，复制和存储第一数据的验证数据缓冲器，基于存储在验证数据缓冲器中的数据编程的多个存储器单元，比较存储在验证数据缓冲器中的数据的比较器 验证数据缓冲器，其具有从编程的存储器单元读出的数据，并输出基于与验证数据缓冲器的比较结果生成的比较数据;以及控制单元，控制程序数据缓冲器，验证数据缓冲器，存储器单元和 所述比较器基于所述第一数据额外编程或验证已成功验证的存储器单元。

    Nonvolatile memory devices capable of reducing data programming time and methods of driving the same
    70.
    发明申请
    Nonvolatile memory devices capable of reducing data programming time and methods of driving the same 失效
    能够减少数据编程时间的非易失性存储器件及其驱动方法

    公开(公告)号：US20080192540A1

    公开(公告)日：2008-08-14

    申请号：US12005366

    申请日：2007-12-27

    Applicant: Jae-Phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

    Inventor： Jae-Phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

    IPC: G11C16/10

    CPC classification number: G11C11/5628

    Abstract: In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.

    Abstract translation: 在驱动非易失性存储器件的方法中，从多个数据状态中确定第一数据状态。 根据确定的第一数据状态来设置同时编程的位的数量，并且对从外部设备输入的数据执行扫描操作以搜索要编程的数据位。 搜索到的数据位被编程为响应于同时编程的位的数量。 对应于第一数据状态的同时被编程的位的数量与对应于多个数据状态中的至少一个数据状态的同时被编程的位的数量不同。

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