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    Semiconductor device with transistor and capacitor and its manufacture method
    61.
    发明授权
    Semiconductor device with transistor and capacitor and its manufacture method 有权
    具有晶体管和电容器的半导体器件及其制造方法

    公开(公告)号：US06849894B2

    公开(公告)日：2005-02-01

    申请号：US10317063

    申请日：2002-12-12

    Applicant: Jun Lin ,  Toshiya Suzuki ,  Katsuhiko Hieda

    Inventor： Jun Lin ,  Toshiya Suzuki ,  Katsuhiko Hieda

    IPC: H01L21/322 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94

    CPC classification number: H01L27/10852 ,  H01L21/31604 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/90

    Abstract: On a semiconductor substrate, a transistor and a capacitor electrically connected to the transistor are formed, the capacitor having two electrodes made of metal and a capacitor dielectric layer between the two electrodes made of oxide dielectric material. A temporary protective film is formed over the capacitor, the temporary protective film covering the capacitor. The semiconductor substrate with the temporary protective film is subjected to a heat treatment in a reducing atmosphere. The temporary protective film is removed. The semiconductor substrate with the temporary protective film removed is subjected to a heat treatment in an inert gas atmosphere or in a vacuum state. A protective film is formed over the capacitor, the protective film covering the capacitor. With these processes, leak current of the capacitor can be reduced.

    Abstract translation: 在半导体衬底上，形成与晶体管电连接的晶体管和电容器，该电容器具有由金属制成的两个电极和由氧化物介电材料制成的两个电极之间的电容器电介质层。 在电容器上形成临时保护膜，临时保护膜覆盖电容器。 具有临时保护膜的半导体衬底在还原气氛中进行热处理。 移除临时保护膜。 将除去了临时保护膜的半导体基板在惰性气体气氛或真空状态下进行热处理。 在电容器上形成保护膜，保护膜覆盖电容器。 通过这些处理，可以减小电容器的漏电流。

    High voltage transistor using P+ buried layer
    62.
    发明授权
    High voltage transistor using P+ buried layer 有权

    公开(公告)号：US06569730B2

    公开(公告)日：2003-05-27

    申请号：US10091990

    申请日：2002-03-06

    Applicant: Jun-Lin Tsai ,  Ruey-Hsin Liu ,  Jei-Feng Hwang ,  Kuo-Chio Liu

    Inventor： Jun-Lin Tsai ,  Ruey-Hsin Liu ,  Jei-Feng Hwang ,  Kuo-Chio Liu

    IPC: H01L218249

    CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/7322

    Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

    Tool holder of hollow taper shank in tool machine
    63.
    发明授权
    Tool holder of hollow taper shank in tool machine 有权
    工具机中空锥柄刀架

    公开(公告)号：US06343903B1

    公开(公告)日：2002-02-05

    申请号：US09499471

    申请日：2000-02-07

    Applicant: Hsiang-Feng Huang ,  Kun-Lung Tsai ,  Wei-Jun Lin ,  Ke-Wu Ou Yang

    Inventor： Hsiang-Feng Huang ,  Kun-Lung Tsai ,  Wei-Jun Lin ,  Ke-Wu Ou Yang

    IPC: B23B31107

    CPC classification number: B23B31/263 ,  B23B29/046 ,  Y10T279/1091 ,  Y10T279/17145 ,  Y10T408/953 ,  Y10T409/309352 ,  Y10T409/30952

    Abstract: A tool holder of the hollow taper shank in a tool machine is disclosed. A resisting block supported by a spring is received within a tool holder. As the short knife is disposed within the tool holder, the elastic force of the spring can be overcome. At first, a plurality of steel balls and a resisting block are pushed inversely until the front edge of an wider portion of the short knife passes through the steel ball. Now, the spring will release the energy from elastic deformation so as to enforce the resisting block to move forwards and outwards so as to return to the original position. Thereby, the knife can be firmly secured.

    Abstract translation: 公开了一种工具机中的中空锥柄的工具架。 由弹簧支撑的抵抗块被容纳在工具架内。 由于短刀配置在工具架内，所以能够克服弹簧的弹力。 首先，多个钢球和抵抗块相反地推动，直到短刀的较宽部分的前边缘通过钢球。 现在，弹簧将释放弹性变形的能量，以便强制抵抗块向前和向外移动以返回到原始位置。 由此，可以牢固地固定刀。

    Integrated circuit polysilicon resistor having a silicide extension to achieve 100 % metal shielding from hydrogen intrusion
    64.
    发明授权
    Integrated circuit polysilicon resistor having a silicide extension to achieve 100 % metal shielding from hydrogen intrusion 有权
    具有硅化物延伸的集成电路多晶硅电阻器，以实现100％金属屏蔽氢侵入

    公开(公告)号：US06340833B1

    公开(公告)日：2002-01-22

    申请号：US09693502

    申请日：2000-10-23

    Applicant: Ruey-Hsin Liu ,  Jun-Lin Tsai ,  Yung-Lung Hsu

    Inventor： Ruey-Hsin Liu ,  Jun-Lin Tsai ,  Yung-Lung Hsu

    IPC: H01L2900

    CPC classification number: H01L28/20 ,  H01L27/0802

    Abstract: A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor. The metal is also patterned to form a metal shield over the resistor to prevent hydrogen diffusion into the resistor. In this invention the spacing between the metal portions contacting the ends of the resistor is aligned over the silicide on the resistor to provide 100% shielding from hydrogen diffusion into the resistor.

    Abstract translation: 通过使用防止氢进入电阻器的硅化物层来实现稳定的高价值多晶硅电阻器。 电阻器也可以集成到自对准硅化物工艺中，用于制造FET而不增加工艺复杂性。 图案化具有帽氧化物的多晶硅层以形成FET栅电极和多晶硅电阻器。 形成了用于FET的轻掺杂源极/漏极，绝缘侧壁间隔物和源极/漏极接触。 盖帽氧化物被图案化以暴露电阻器的一端，并且帽状氧化物从栅电极移除。 沉积和退火难熔金属以形成硅化物FET并同时在电阻器的末端形成硅化物。 未反应的金属被蚀刻。 沉积层间电介质层，并且在电阻器的两端形成与金属插塞的接触孔。 沉积金属以形成第一级金属互连，其也提供与电阻器两端的接触。 金属也被图案化以在电阻器上形成金属屏蔽，以防止氢扩散到电阻器中。 在本发明中，接触电阻器端部的金属部分之间的间隔在电阻器上的硅化物上排列，以提供100％的阻挡氢扩散到电阻器中的屏蔽。

    Voltage sensing circuit
    65.
    发明授权
    Voltage sensing circuit 有权
    电压检测电路

    公开(公告)号：US6147529A

    公开(公告)日：2000-11-14

    申请号：US207472

    申请日：1998-12-08

    Applicant: Jun-Lin Yeh ,  Chien-Chung Chen

    Inventor： Jun-Lin Yeh ,  Chien-Chung Chen

    IPC: G05F3/24 ,  H03K5/08 ,  H03K17/22 ,  H03K5/22

    CPC classification number: H03K17/223 ,  G05F3/242 ,  H03K5/08

    Abstract: A voltage sensing circuit consists of a sensing node, a transistor of a first conductivity type, a diode-like device, a first reference voltage source, a transistor of a second conductivity type, and a second reference voltage source. The transistor of a first conductivity type is configured with one source/drain receiving an input voltage signal and another source/drain connected to the sensing node. The diode-like device receives the input voltage signal and, accordingly, generates a voltage-dropped signal. The first reference voltage source is connected to a gate of the transistor of the first conductivity type. The transistor of a second conductivity type is configured with one source/drain connected to the sensing node and a gate receiving the voltage-dropped signal. The second reference voltage source is connected to another source/drain of the transistor of the second conductivity type.

    Abstract translation: 电压感测电路由感测节点，第一导电类型的晶体管，二极管类器件，第一参考电压源，第二导电类型的晶体管和第二参考电压源组成。 第一导电类型的晶体管配置有接收输入电压信号的一个源极/漏极和连接到感测节点的另一个源极/漏极。 二极管状器件接收输入电压信号，因此产生降压信号。 第一参考电压源连接到第一导电类型的晶体管的栅极。 第二导电类型的晶体管配置有连接到感测节点的一个源极/漏极和接收电压下降信号的栅极。 第二参考电压源连接到第二导电类型晶体管的另一个源极/漏极。

    Uniform sidewall profile etch method for forming low contact leakage schottky diode contact
    66.
    发明授权
    Uniform sidewall profile etch method for forming low contact leakage schottky diode contact 有权

    公开(公告)号：US6096629A

    公开(公告)日：2000-08-01

    申请号：US187301

    申请日：1998-11-05

    Applicant: Jun-Lin Tsai ,  Yen-Shih Ho

    Inventor： Jun-Lin Tsai ,  Yen-Shih Ho

    IPC: H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H01L21/28

    CPC classification number: H01L21/28537 ,  H01L21/31116 ,  H01L21/76804

    Abstract: A method for forming a Schottky diode. There is first provided a silicon layer. There is then formed upon the silicon layer an anisotropically patterned first dielectric layer which defines a Schottky diode contact region of the silicon layer. There is then formed and aligned upon the anisotropically patterned first dielectric layer a patterned second dielectric layer which is formed of a thermally reflowable material. There is then reflowed thermally the patterned second dielectric layer to form a thermally reflowed patterned second dielectric layer having a uniform sidewall profile with respect to the anisotropically patterned first dielectric layer while simultaneously forming a thermal silicon oxide layer upon the Schottky diode contact region of the silicon layer. There is then etched while employing a first etch method the thermal silicon oxide layer from the Schottky diode contact region of the silicon layer while preserving the uniform sidewall profile of the thermally reflowed patterned second dielectric layer with respect to the anisotropically patterned first dielectric layer. There is then formed and thermally annealed upon the thermally reflowed patterned second dielectric layer and the Schottky diode contact region of the silicon layer a metal silicide forming metal layer to form in a self aligned fashion a metal silicide layer upon the Schottky diode contact region of the silicon layer, a protective oxide surface layer upon the metal silicide layer and a metal silicide forming metal layer residue upon the thermally reflowed patterned second dielectric layer. There is then stripped from the thermally reflowed patterned second dielectric layer the metal silicide forming metal layer residue. Finally, there is then etched while employing a second etch method the protective oxide surface layer from the metal silicide layer, where the second etch method also preserves the uniform sidewall profile of the thermally reflowed patterned second dielectric layer with respect to the anisotropically patterned first dielectric layer.

    Floating gate memory array device with improved program and read performance
    67.
    发明授权
    Floating gate memory array device with improved program and read performance 失效
    浮栅存储器阵列器件具有改进的程序和读取性能

    公开(公告)号：US5862073A

    公开(公告)日：1999-01-19

    申请号：US931065

    申请日：1997-09-15

    Applicant: Jun-Lin Yeh ,  Ya-Chun Chang

    Inventor： Jun-Lin Yeh ,  Ya-Chun Chang

    IPC: G11C16/04 ,  G11C16/08 ,  G11C7/00

    CPC classification number: G11C16/08 ,  G11C16/0416

    Abstract: A semiconductor memory array and method for use in a memory device in which the location of a memory cell in the array is specified by row address and column address decoders. The memory cells may be floating gate memory cells in which data is programmed by hot carrier injection and erased by Fowler-Nordheim tunneling. The array includes bit lines connected to the column address decoder, and word lines and N+ diffusion source lines connected to the row address decoder. Each memory cell has a gate connected to a word line, a drain connected to a bit line and a source connected to the N+ diffusion source line. A low resistance source line formed of metal II or other conductive material is arranged adjacent to each N+ source line and is electrically connected thereto at one or more locations via interconnecting straps. The low resistance source lines serve to reduce the voltage drop across the N+ diffusion source lines during program operations and provide an improved ground connection during read operations. The word lines are grouped into pairs of even and odd word lines and each pair makes up the minimum program unit or page. The page is also the minimum erase unit, such that adjacent even and odd word lines are erased simultaneously. The voltage applied to a given word line during a read operation may be supplied by a word line clamping circuit which limits gate disturbances resulting from fluctuations in supply voltage.

    Abstract translation: 一种在存储器件中使用的半导体存储器阵列和方法，其中阵列中的存储单元的位置由行地址和列地址解码器指定。 存储器单元可以是浮动栅极存储单元，其中通过热载流子注入来编程数据，并通过Fowler-Nordheim隧道擦除数据。 阵列包括连接到列地址解码器的位线，以及连接到行地址解码器的字线和N +扩散源线。 每个存储单元具有连接到字线的栅极，连接到位线的漏极和连接到N +扩散源线的源极。 由金属II或其他导电材料形成的低电阻源极线布置成与每个N +源极线相邻，并且通过互连带在一个或多个位置处电连接到其上。 低电阻源线用于在编程操作期间减小N +扩散源线上的电压降，并在读取操作期间提供改进的接地连接。 字线被分组成偶数和奇数字线对，每对组成最小程序单元或页面。 该页面也是最小擦除单元，使得相邻的偶数和奇数字线同时被擦除。 在读取操作期间施加到给定字线的电压可以由限制由电源电压波动引起的栅极干扰的字线钳位电路提供。

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