公开(公告)号：US07245140B2

公开(公告)日：2007-07-17

申请号：US10987706

申请日：2004-11-12

Applicant: Jung Sunwoo ,  Jung-Bae Lee

Inventor： Jung Sunwoo ,  Jung-Bae Lee

IPC: G01R31/26 ,  G11C7/00

CPC classification number: G01R31/31713 ,  G01R31/31723

Abstract: A semiconductor device includes an ODT (on die termination) pin coupled to a tester that applies a tester termination control signal thereon. The semiconductor device also includes a measure path that transmits the tester termination control signal from the ODT pin to an ODT circuit during measurement of a parameter of the semiconductor device. The ODT pin and the measure path advantageously allow for control of the ODT circuit by the tester for more accurate parameter characterization.

Abstract translation: 半导体器件包括耦合到测试器的ODT（管芯端子）引脚上的测试器端接控制信号。 半导体器件还包括测量路径，该测量路径在测量半导体器件的参数期间将测试器终止控制信号从ODT引脚传输到ODT电路。 ODT引脚和测量路径有利地允许由测试仪控制ODT电路以获得更准确的参数表征。

公开(公告)号：US07227796B2

公开(公告)日：2007-06-05

申请号：US10750093

申请日：2003-12-31

Applicant: Jung-Bae Lee ,  Hoe-Ju Chung

Inventor： Jung-Bae Lee ,  Hoe-Ju Chung

IPC: G11C5/02

CPC classification number: G06F13/1673

Abstract: The invention provides an improved memory system that addresses signal degradation due to transmission line effects. The improved memory system includes a first buffer, at least one first memory device coupled to the first buffer, and a plurality of signal traces. The first buffer and memory device are mounted on a motherboard. Likewise, the plurality of signal traces is routed on the motherboard. Doing so eliminates stub loads that cause signal reflection that, in turn, result in signal degradation.

Abstract translation: 本发明提供了一种改进的存储器系统，其解决了由于传输线效应引起的信号劣化。 改进的存储器系统包括第一缓冲器，耦合到第一缓冲器的至少一个第一存储器件和多个信号迹线。 第一个缓冲器和存储器件安装在主板上。 同样地，多个信号迹线在主板上路由。 这样做可以消除引起信号反射的短线负载，从而导致信号衰减。

公开(公告)号：US20070075745A1

公开(公告)日：2007-04-05

申请号：US11540345

申请日：2006-09-29

Applicant: In Dal Song ,  Jung Bae Lee

Inventor： In Dal Song ,  Jung Bae Lee

IPC: H03K19/094

CPC classification number: H03K19/017545 ,  H03K19/017581 ,  H04L25/0278 ,  H04L25/0286

Abstract: An output driver controls impedance using a mode register set. The output driver includes a main driving circuit that outputs and drives a main signal based on a data signal to a predetermined transmission line, an auxiliary driving circuit that outputs and drives an auxiliary signal to the transmission line, and a mode register set. The mode register set generates an impedance control signal group, a driving width control signal group and a delay control signal group. The amount of an auxiliary impedance (SIM), and the driving width and driving time point of an auxiliary signal (XSDR) can be controlled using the impedance control signal group, the driving width control signal group and the delay control signal group. Therefore, in accordance with the output driver of the present invention, the amount of output impedance (OIM), a pre-emphasis width and a pre-emphasis time point can be readily controlled, and the efficiency of the transmission of an output signal to a reception system is improved.

Abstract translation: 输出驱动器使用模式寄存器组控制阻抗。 输出驱动器包括：主驱动电路，其将基于数据信号的主信号输出并驱动到预定传输线;辅助驱动电路，其向传输线输出并驱动辅助信号;以及模式寄存器组。 模式寄存器组产生阻抗控制信号组，驱动宽度控制信号组和延迟控制信号组。 可以使用阻抗控制信号组，驱动宽度控制信号组和延迟控制信号组来控制辅助阻抗（SIM）的量以及辅助信号（XSDR）的驱动宽度和驱动时间点。 因此，根据本发明的输出驱动器，可以容易地控制输出阻抗（OIM）的量，预加重宽度和预加重时间点，并且输出信号的传输效率 改善了接收系统。

公开(公告)号：US07196941B2

公开(公告)日：2007-03-27

申请号：US10798469

申请日：2004-03-11

Applicant: Yun-Sang Lee ,  Jung-Bae Lee ,  Jung-Hwan Choi

Inventor： Yun-Sang Lee ,  Jung-Bae Lee ,  Jung-Hwan Choi

IPC: G11C7/10

CPC classification number: G11C7/18 ,  G11C7/10 ,  G11C7/1021 ,  G11C7/1048 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A semiconductor memory device and a method for writing and reading data to and from the same comprises a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs, a predetermined number of write line pairs, a predetermined number of read line pairs, a plurality of write column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of write line pair during a write operation, and a plurality of read column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of read line pairs during a read operation. Accordingly, it is possible to input and output data simultaneously through data input pads and data output pads.

Abstract translation: 一种半导体存储器件和用于从其读取和读取数据的方法包括：存储单元阵列，包括连接在多个字线和多个位线对之间的多个存储器单元，预定数量的写入线对 ，预定数量的读线对，用于在写入操作期间在多个位线对与预定数量的写入线对之间传送数据的多个写入列选择门和用于发送数据的多个读取列选择门 在读取操作期间在多个位线对与预定数量的读取线对之间。 因此，可以通过数据输入焊盘和数据输出焊盘同时输入和输出数据。

公开(公告)号：US20060132657A1

公开(公告)日：2006-06-22

申请号：US11268623

申请日：2005-11-08

Applicant: Jung-bae Lee ,  Jae-hong Park

Inventor： Jung-bae Lee ,  Jae-hong Park

IPC: H04N5/50

CPC classification number: G09G5/003 ,  G09G2310/0229 ,  G09G2320/08 ,  H04N5/21 ,  H04N5/44513 ,  H04N7/012 ,  H04N21/4402 ,  H04N21/485

Abstract: A display apparatus having a display. The display apparatus includes a video signal processor having a processor to process an input video signal and a picture quality improving part to improve picture quality of the processed video signal. The video signal processor processes the video signal through a path that includes a signal processing path to selectively bypass the picture quality improving part. The display apparatus further includes a selection input part through which the user selects a bypass mode corresponding to the signal processing path. Finally, the display apparatus has a controller controlling the video signal processor to output the video signal processed through the processor to the display after bypassing the picture quality improving part when the user selects the bypass mode through the selection input part. Thus, the picture quality improving function may be omitted to thereby reduce signal processing time.

Abstract translation: 具有显示器的显示装置。 显示装置包括具有处理输入视频信号的处理器和图像质量改善部分的视频信号处理器，以改善处理的视频信号的图像质量。 视频信号处理器通过包括信号处理路径的路径处理视频信号，以选择性地绕过图像质量改善部分。 显示装置还包括选择输入部，用户通过该选择输入部选择与信号处理路径对应的旁路模式。 最后，当用户通过选择输入部分选择旁路模式时，显示装置具有控制视频信号处理器以将通过处理器处理的视频信号输出到显示器的旁路图像质量改善部分之后的控制器。 因此，可以省略图像质量改善功能，从而减少信号处理时间。

公开(公告)号：US06879536B2

公开(公告)日：2005-04-12

申请号：US10453221

申请日：2003-06-03

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/406

CPC classification number: G11C7/1063 ,  G11C7/1051 ,  G11C11/406 ,  G11C11/40615

Abstract: A semiconductor memory device includes an oscillator for generating an oscillator output signal; a refresh timer for generating a refresh pulse in response to predetermined first and second control signals, the oscillator output signal, and an external clock signal; a mode register set (MRS) unit for generating the first and second control signals in response to an address signal and an external command, the first control signal controlling time when the refresh pulse is generated by the refresh timer and the second control signal resetting the refresh timer; and a refresh controller for generating a refresh control signal in response to the refresh pulse, the refresh control signal refreshing a memory cell, wherein the refresh control signal is output as a refresh flag while the memory is refreshed.

Abstract translation: 半导体存储器件包括用于产生振荡器输出信号的振荡器; 刷新定时器，用于响应于预定的第一和第二控制信号，所述振荡器输出信号和外部时钟信号产生刷新脉冲; 模式寄存器组（MRS）单元，用于响应于地址信号和外部命令产生第一和第二控制信号，第一控制信号控制刷新脉冲由刷新定时器产生的时间，第二控制信号重新设置 刷新定时器; 以及刷新控制器，用于响应刷新脉冲产生刷新控制信号，刷新控制信号刷新存储单元，其中刷新控制信号作为刷新标志被输出，同时刷新存储器。

公开(公告)号：US06826114B2

公开(公告)日：2004-11-30

申请号：US10624783

申请日：2003-07-22

Applicant: Jung-bae Lee ,  Won-chang Jung

Inventor： Jung-bae Lee ,  Won-chang Jung

IPC: G11C800

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096

Abstract: Provided are a reset circuit of a data path using a clock enable signal, a reset method and a semiconductor memory device having the reset circuit. The reset circuit includes an external voltage detector and a second reset signal generator, in which the second reset signal is used to reset a block related to a data path of the semiconductor memory device. The external voltage detector detects the level of an external voltage and generates a first reset signal. The second reset signal generator performs a logical sum of an external signal, which is externally input, and the first reset signal, and generates a second reset signal. The first reset signal is used to reset blocks other than the blocks related to the data path. The external signal is a clock enable signal. In the soft reset, the blocks related to the data path are reset using the external signal which is applied at a certain level. Thus, data conflicts or ineffective data can be prevented in executing operations according to the read/write commands which are applied after the soft reset.

Abstract translation: 提供了使用时钟使能信号的数据路径的复位电路，复位方法和具有复位电路的半导体存储器件。 复位电路包括外部电压检测器和第二复位信号发生器，其中第二复位信号用于复位与半导体存储器件的数据路径有关的块。 外部电压检测器检测外部电压的电平并产生第一复位信号。 第二复位信号发生器执行外部输入的外部信号与第一复位信号的逻辑和，并产生第二复位信号。 第一复位信号用于复位与数据路径相关的块以外的块。 外部信号是时钟使能信号。 在软复位中，与数据通路相关的模块使用外部信号进行复位，该外部信号以一定的电平施加。 因此，根据在软复位之后应用的读/写命令执行操作时，可以防止数据冲突或无效数据。

公开(公告)号：US06728162B2

公开(公告)日：2004-04-27

申请号：US10081546

申请日：2002-02-21

Applicant: Jung-bae Lee ,  One-gyun La

Inventor： Jung-bae Lee ,  One-gyun La

IPC: G11C800

CPC classification number: G11C7/1093 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087

Abstract: A circuit for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.

Abstract translation: 一种用于接收要写入同步半导体存储器件的数据的电路，包括：第一组锁存器，用于在内部选通信号转换时接收n位数据; 计数器，用于对内部选通信号的转换次数进行计数，并在计数一串内部选通信号的结束时输出指示信号; 第二组锁存器，用于接收第一组锁存器的输出，第二组锁存器由指示信号计时; 以及第三组锁存器，用于接收第二组锁存器的输出，第三组锁存器由从系统时钟导出的时钟信号计时。

公开(公告)号：US06636446B2

公开(公告)日：2003-10-21

申请号：US10154734

申请日：2002-05-24

Applicant: Chan-Yong Lee ,  Jung-Bae Lee

Inventor： Chan-Yong Lee ,  Jung-Bae Lee

IPC: G11C700

CPC classification number: G11C7/1066 ,  G11C7/22 ,  G11C11/4082 ,  G11C2207/2218

Abstract: A semiconductor memory device capable of improving common bus efficiency is disclosed. The device comprises an address shifting circuit for delaying an address by an n+m number of clock cycles in response to a clock signal, a control signal generating circuit for combining a column address strobe (CAS) latency of n-value and one of first and second operation signals to generate a control signal, and a switching circuit for outputting the address delayed by the n+m number of clock cycles output from the address shifting circuit in response to the control signal. The first operation signal indicates that the n-value of the CAS latency is less than a predetermined value and write latency is fixed. The second operation signal indicates that the n-value of the CAS latency is equal to or greater than the predetermined value and the write latency is variable.

Abstract translation: 公开了能够提高公共总线效率的半导体存储器件。 该装置包括地址移位电路，用于响应于时钟信号将地址延迟n + m个时钟周期;控制信号发生电路，用于组合n值的列地址选通（CAS）等待时间和第一 以及第二操作信号以产生控制信号，以及切换电路，用于响应于控制信号，输出延迟了从地址移位电路输出的n + m个时钟周期的地址。 第一操作信号指示CAS等待时间的n值小于预定值，并且写等待时间是固定的。 第二操作信号指示CAS延迟的n值等于或大于预定值，并且写入等待时间是可变的。

公开(公告)号：US06272068B1

公开(公告)日：2001-08-07

申请号：US09667379

申请日：2000-09-22

Applicant: One-gyun La ,  Jung-bae Lee ,  Si-yeol Lee

Inventor： One-gyun La ,  Jung-bae Lee ,  Si-yeol Lee

IPC: G11C800

CPC classification number: G11C7/1093 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/222 ,  G11C29/48

Abstract: Integrated circuit memory devices that utilize preferred masking techniques include a memory cell array and a mask signal generator that generates first and second internal data masking signals in response to at least one single data rate mode signal. A data controller is also provided to pass input write data to the memory cell array when the first and second internal data masking signals are inactive and mask at least a portion of the input write data from the memory cell array when one of the first and second internal data masking signals is active. This ability to mask data facilitates operation of the memory device in a specialized single data rate mode for testing using conventional test equipment.

Abstract translation: 利用优选掩蔽技术的集成电路存储器件包括存储单元阵列和屏蔽信号发生器，其响应于至少一个单个数据速率模式信号产生第一和第二内部数据屏蔽信号。 还提供数据控制器，用于当第一和第二内部数据屏蔽信号不活动时将输入写入数据传送到存储单元阵列，并且当第一和第二数据屏蔽信号中的一个第一和第二 内部数据屏蔽信号有效。 掩蔽数据的这种能力有助于以专门的单数据速率模式进行存储器件的操作，以便使用常规测试设备进行测试。