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    Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities
    62.
    发明申请
    Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities 有权
    使用具有高应力特性的绝缘层的CMOS集成电路的形成方法来改善NMOS和PMOS晶体管载体的迁移率

    公开(公告)号：US20090124093A1

    公开(公告)日：2009-05-14

    申请号：US12353519

    申请日：2009-01-14

    Applicant: Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

    Inventor： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

    IPC: H01L21/469

    CPC classification number: H01L21/823807 ,  H01L29/7843

    Abstract: A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

    Abstract translation: CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。 提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。 特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

    Structure of a CMOS image sensor and method for fabricating the same
    63.
    发明授权
    Structure of a CMOS image sensor and method for fabricating the same 有权
    CMOS图像传感器的结构及其制造方法

    公开(公告)号：US07400003B2

    公开(公告)日：2008-07-15

    申请号：US10998803

    申请日：2004-11-30

    Applicant: Soo-Geun Lee ,  Ki-Chul Park ,  Kyoung-Woo Lee

    Inventor： Soo-Geun Lee ,  Ki-Chul Park ,  Kyoung-Woo Lee

    IPC: H01L31/062

    CPC classification number: H01L23/53238 ,  G01R31/2829 ,  H01L21/76805 ,  H01L27/14603 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687 ,  H01L31/022408 ,  H01L2924/0002 ,  H04N17/002 ,  H01L2924/00

    Abstract: An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

    Abstract translation: 图像传感器装置及其形成方法包括形成在基板中的光电二极管，与光电二极管电连接的至少一个电互连线，具有光入口的光通路，光通路与光电二极管对准， 位于光通道的光入口之上的滤色器和位于滤光器上的透镜与光通路对准，其中至少一个电互连线包括铜互连结构，铜互连结构具有层叠形式的多个层间电介质层， 相邻的层间电介质层之间的扩散阻挡层和铜互连结构与多个层间电介质层之间的阻挡金属层以及介于其间的扩散阻挡层。 如果从光电二极管上方去除阻挡金属层，则图像传感器装置可以采用铜互连。

    Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization
    64.
    发明授权
    Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization 有权
    用于形成用于铜基金属化的氢填充沟槽衬垫的物理气相沉积方法

    公开(公告)号：US07387962B2

    公开(公告)日：2008-06-17

    申请号：US11251947

    申请日：2005-10-17

    Applicant: Kyoung-Woo Lee ,  Seung-Man Choi

    Inventor： Kyoung-Woo Lee ,  Seung-Man Choi

    IPC: H01L21/44

    CPC classification number: H01L21/2855 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76873

    Abstract: Copper-based metallization is formed in a trench on an integrated circuit substrate by forming a liner of refractory metal in the trench using physical vapor deposition, forming a copper plating seed layer on the liner using physical vapor deposition and then plating copper on the copper plating seed layer. Prior to plating copper on the copper plating seed layer, the liner and/or copper plating seed layer is stuffed with hydrogen, for example by exposing the liner and/or copper plating seed layer to a hydrogen-containing plasma during and/or after formation of the liner and/or copper plating seed layer. Related structures also are disclosed.

    Abstract translation: 通过使用物理气相沉积在沟槽中形成难熔金属的衬垫，在集成电路衬底的沟槽中形成铜基金属化，使用物理气相沉积在衬套上形成铜电镀种子层，然后在铜电镀上镀铜 种子层。 在镀铜种子层上镀铜之前，衬里和/或铜电镀种子层被填充氢，例如通过在形成期间和/或之后将衬里和/或铜电镀种子层暴露于含氢等离子体 的衬里和/或铜电镀种子层。 还公开了相关结构。

    Method of forming a via contact structure using a dual damascene process
    66.
    发明授权
    Method of forming a via contact structure using a dual damascene process 有权
    使用双镶嵌工艺形成通孔接触结构的方法

    公开(公告)号：US07307014B2

    公开(公告)日：2007-12-11

    申请号：US11099534

    申请日：2005-04-06

    Applicant: Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

    Inventor： Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

    IPC: H01L21/4763

    CPC classification number: H01L21/76808

    Abstract: A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.

    Abstract translation: 公开了一种使用双镶嵌工艺形成通孔接触结构的方法。 根据一个实施例，在形成预通孔期间，在绝缘中间层上形成牺牲层。 牺牲层具有与随后的沟槽形成过程中填充预通孔的层相同的组成。 在进行沟槽形成处理之后，同时去除牺牲层和填充预通孔的层。 根据另一实施例，在形成预通孔期间，在绝缘中间层上形成薄封盖氧化物层。 在进行沟槽形成处理之后，薄层氧化物层与牺牲层一起被去除。

    Dual damascene interconnection with metal-insulator-metal-capacitor and method of fabricating the same
    67.
    发明授权
    Dual damascene interconnection with metal-insulator-metal-capacitor and method of fabricating the same 失效
    金属绝缘体 - 金属电容器的双镶嵌互连及其制造方法

    公开(公告)号：US07279733B2

    公开(公告)日：2007-10-09

    申请号：US10799292

    申请日：2004-03-12

    Applicant: Kyoung-woo Lee ,  Soo-geun Lee

    Inventor： Kyoung-woo Lee ,  Soo-geun Lee

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L21/76807 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.

    Abstract translation: 提供了一种与金属 - 绝缘体 - 金属（MIM）电容器的双镶嵌互连及其制造方法。 在该结构中，在通孔级IMD上形成MIM电容器。 在形成通孔级IMD之后，当形成MIM电容器图形化的对准键时，形成通孔，以连接MIM电容器的下电极和配置在通孔级IMD下的互连。 此外，在双镶嵌工艺期间，MIM电容器的上电极直接连接到上金属互连。

    Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization, and resultant structures
    69.
    发明申请
    Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization, and resultant structures 有权
    用于形成用于铜基金属化的氢填充沟槽衬垫的物理气相沉积方法，以及所得结构

    公开(公告)号：US20070087567A1

    公开(公告)日：2007-04-19

    申请号：US11251947

    申请日：2005-10-17

    Applicant: Kyoung-Woo Lee ,  Seung-Man Choi

    Inventor： Kyoung-Woo Lee ,  Seung-Man Choi

    IPC: H01L21/44 ,  H01L21/4763

    CPC classification number: H01L21/2855 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76873

    Abstract: Copper-based metallization is formed in a trench on an integrated circuit substrate by forming a liner of refractory metal in the trench using physical vapor deposition, forming a copper plating seed layer on the liner using physical vapor deposition and then plating copper on the copper plating seed layer. Prior to plating copper on the copper plating seed layer, the liner and/or copper plating seed layer is stuffed with hydrogen, for example by exposing the liner and/or copper plating seed layer to a hydrogen-containing plasma during and/or after formation of the liner and/or copper plating seed layer. Related structures also are disclosed.

    Abstract translation: 通过使用物理气相沉积在沟槽中形成难熔金属的衬垫，在集成电路衬底的沟槽中形成铜基金属化，使用物理气相沉积在衬套上形成铜电镀种子层，然后在铜电镀上镀铜 种子层。 在镀铜种子层上镀铜之前，衬里和/或铜电镀种子层被填充氢，例如通过在形成期间和/或之后将衬里和/或铜电镀种子层暴露于含氢等离子体 的衬里和/或铜电镀种子层。 还公开了相关结构。

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