公开(公告)号：US06078492A

公开(公告)日：2000-06-20

申请号：US128364

申请日：1998-08-03

Applicant: Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

Inventor： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01G4/30 ,  H01G4/008

CPC classification number: H01L27/10852 ,  H01L28/82

Abstract: A structure of a capacitor includes two gates and a commonly used source/drain region on a substrate. Then, a pitted self align contact window (PSACW) partly exposes the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are over the PSACW. Then a dielectric thin film with a material having high dielectric constant is over the lower electrode. Then, an upper electrode is over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.

Abstract translation: 电容器的结构包括两个栅极和在衬底上的常用源极/漏极区域。 然后，凹陷的自对准接触窗口（PSACW）部分地暴露常用的源极/漏极区域。 然后电容器的胶/阻挡层和下电极在PSACW之上。 然后，具有高介电常数的材料的电介质薄膜在下电极之上。 然后，上电极在电介质薄膜的上方，以完成电容器，该电容器具有类似于PSACW形状的金属绝缘体金属的结构。

公开(公告)号：US5956598A

公开(公告)日：1999-09-21

申请号：US164736

申请日：1998-10-01

Applicant: Kuo-Tai Huang ,  Gwo-Shii Yang ,  Tri-Rung Yew ,  Water Lur

Inventor： Kuo-Tai Huang ,  Gwo-Shii Yang ,  Tri-Rung Yew ,  Water Lur

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure with a rounded corner in integrated circuits through a rapid thermal process (RTP). In the fabrication of the STI structure, a sharp corner is often undesirably formed. This sharp corner , if not eliminated, causes the occurrence of a leakage current when the resultant IC device is in operation that significantly degrades the performance of the resultant IC device. To eliminate this sharp corner , an RTP is performed at a temperature of above 1,100.degree. C., which temperature is higher than the glass transition temperature of the substrate, for about 1 to 2 minutes. The result is that the surface of the substrate is oxidized into an sacrificial oxide layer and the sharp corner is deformed into a rounded shape with a larger convex radius of curvature. This allows the problems arising from the existence of the sharp corner to be substantially eliminated. Compared to the prior art, this method not only is more simplified in process, but also allows a considerable saving in thermal budget, which makes this method more cost-effective to implement than the prior art.

Abstract translation: 提供半导体制造方法，用于通过快速热处理（RTP）在集成电路中制造具有圆角的浅沟槽隔离（STI）结构。 在STI结构的制造中，通常不希望地形成尖锐的拐角。 如果不消除这个尖角，则当所得到的IC器件运行时会导致泄漏电流的发生，这显着降低了所得IC器件的性能。 为了消除这个尖角，RTP在高于1100℃的温度下进行，该温度高于基板的玻璃化转变温度约1至2分钟。 其结果是，衬底的表面被氧化成牺牲氧化物层，并且尖角变形为具有较大凸曲率半径的圆形形状。 这允许基本上消除由尖角存在引起的问题。 与现有技术相比，该方法不仅在过程中更简化，而且还可以大大节省热预算，这使得该方法比现有技术更具成本效益。

公开(公告)号：US20240293972A1

公开(公告)日：2024-09-05

申请号：US18431818

申请日：2024-02-02

Applicant: Kuo-Tai Huang

Inventor： Kuo-Tai Huang

IPC: B29C64/379 ,  B33Y40/00

CPC classification number: B29C64/379 ,  B33Y40/00

Abstract: A print cutting machine includes a main body, a moving unit, a cutting unit, a receiving unit, and a workpiece unit. The main body is provided with a receiving space, a first stand, two first slide rails, and two second slide rails. The moving unit is movably mounted on the first stand and includes a second stand, a moving seat, and a fitting seat. The second stand slides on the first stand linearly. The moving seat is moved on the second stand linearly. The fitting seat is mounted on the moving seat. The cutting unit is mounted on the two second slide rails. The receiving unit is received in the receiving space. The workpiece unit is assembled with the moving unit and includes a base, at least one molded portion mounted on the base, and at least one cutout.

公开(公告)号：US11703615B2

公开(公告)日：2023-07-18

申请号：US17212357

申请日：2021-03-25

Applicant: Chih-Wei Yuan ,  Kuo-Tai Huang

Inventor： Chi-Chou Yuan

IPC: B05D1/18 ,  G02B3/04 ,  G02B1/10 ,  B05D3/02 ,  G02C7/02

CPC classification number: G02B3/04 ,  B05D1/18 ,  B05D3/0263 ,  G02B1/10 ,  G02C7/02

Abstract: The present invention relates to a manufacturing method for a mid-infrared lens, which includes the following steps: placing a lens in the path of a far-infrared radiation source, enabling the lens to receive the far infrared rays; immersing the lens in a hardening liquid, causing the hardening liquid to coat the lens, wherein the hardening liquid is an intermixture of silicone and isopropanol or an intermixture of silicone and methanol, and a far-infrared material or a far-infrared composite material is additionally added to the hardening liquid; placing the lens coated with the hardening liquid in a drying space to dry, causing the hardening liquid to dry and harden and form a hardened layer on the surface of the lens. The temperature of the drying space lies between 80 and 120° C., and the drying time lies between 1 and 10 hours.

公开(公告)号：US08836038B2

公开(公告)日：2014-09-16

申请号：US12883241

申请日：2010-09-16

Applicant: Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Tze-Liang Lee

Inventor： Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Tze-Liang Lee

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。 第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。 第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

公开(公告)号：US08450161B2

公开(公告)日：2013-05-28

申请号：US13465551

申请日：2012-05-07

Applicant: Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

Inventor： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC: H01L21/00 ,  H01L21/02

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US08383502B2

公开(公告)日：2013-02-26

申请号：US13186572

申请日：2011-07-20

Applicant: Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Jr Jung Lin ,  Yi-Shien Mor ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Jr Jung Lin ,  Yi-Shien Mor ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/82385 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.

Abstract translation: 制造半导体器件的方法包括提供具有第一有源区和第二有源区的半导体衬底，在高k电介质层上形成第一金属层，去除第二有源区中的第一金属层的至少一部分 在第一有源区的第一金属层上形成第二金属层，在第二有源区的高k电介质层上形成第二金属层，然后在第二金属层上形成硅层。 该方法还包括从第一栅极堆叠中去除硅层，从而形成第一沟槽并从第二栅极堆叠形成第二沟槽，并且在第一沟槽中的第二金属层上方形成第三金属层，并在第二金属 在第二沟槽中。

公开(公告)号：US20110275212A1

公开(公告)日：2011-11-10

申请号：US13186572

申请日：2011-07-20

Applicant: Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Jr Jung Lin ,  Yi-Shien Mor ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Jr Jung Lin ,  Yi-Shien Mor ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen

IPC: H01L21/28

CPC classification number: H01L21/82385 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.

Abstract translation: 制造半导体器件的方法包括提供具有第一有源区和第二有源区的半导体衬底，在高k电介质层上形成第一金属层，去除第二有源区中的第一金属层的至少一部分 在第一有源区的第一金属层上形成第二金属层，在第二有源区的高k电介质层上形成第二金属层，然后在第二金属层上形成硅层。 该方法还包括从第一栅极堆叠中去除硅层，从而形成第一沟槽并从第二栅极堆叠形成第二沟槽，并且在第一沟槽中的第二金属层上方形成第三金属层，并在第二金属 在第二沟槽中。

公开(公告)号：US08003507B2

公开(公告)日：2011-08-23

申请号：US12478509

申请日：2009-06-04

Applicant: Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Jr Jung Lin ,  Yi-Shien Mor ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Jr Jung Lin ,  Yi-Shien Mor ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/82385 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer over the high-k dielectric layer, the first metal layer having a first work function, removing a portion of the first metal layer in the second active region, thereafter, forming a semiconductor layer over the first metal layer in the first active region and over the partially removed first metal layer in the second active region, forming a first gate stack in the first active region and a second gate stack in the second active region, removing the semiconductor layer from the first gate stack and from the second gate stack, and forming a second metal layer on the first metal layer in the first gate stack and on the partially removed first metal layer in the second gate stack, the second metal layer having a second work function.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成第一金属层，第一金属层具有第一 在第二有源区中除去第一金属层的一部分，然后在第一有源区中的第一金属层上方和在第二有源区中的部分去除的第一金属层上方形成半导体层，形成第一 在第一有源区中的栅极堆叠和第二有源区中的第二栅极堆叠，从第一栅极堆叠和第二栅极堆叠中去除半导体层，以及在第一栅极堆叠中的第一金属层上形成第二金属层 并且在第二栅极堆叠中部分去除的第一金属层上，第二金属层具有第二功函数。

公开(公告)号：US20100068861A1

公开(公告)日：2010-03-18

申请号：US12339483

申请日：2008-12-19

Applicant: Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Joseph Lin ,  Jr Jung Lin ,  Yu Chao Lin ,  Chao-Cheng Chen ,  Kuo-Tai Huang

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Joseph Lin ,  Jr Jung Lin ,  Yu Chao Lin ,  Chao-Cheng Chen ,  Kuo-Tai Huang

IPC: H01L21/8234 ,  H01L21/28

CPC classification number: H01L29/7848 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636

Abstract: Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.

Abstract translation: 提供了一种半导体制造方法，包括允许在制造过程期间限定和/或修改栅极结构高度的工艺步骤。 栅极结构高度可以在制造期间的一个或多个阶段被修改（例如减小），通过蚀刻包括在栅极结构中的多晶硅层的一部分。 该方法包括在衬底上形成覆盖层并覆盖栅极结构。 将涂层回蚀刻以露出栅极结构的一部分。 蚀刻栅极结构（例如，多晶硅）以降低栅极结构的高度。