公开(公告)号：US20070283303A1

公开(公告)日：2007-12-06

申请号：US11742287

申请日：2007-04-30

申请人： Shigeo OHSHIMA ,  Kiminobu Suzuki

发明人： Shigeo OHSHIMA ,  Kiminobu Suzuki

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The verification equipment of a semiconductor integrated circuit in the present invention is included with a circuit net list extraction section that extracts the net list of a circuit, a circuit simulation execution section that executes a circuit simulation, based on the extracted net list, a finite impedance judgment section that judges existence or nonexistence of finite impedances, a floating error terminal judgment section that judges existence or nonexistence of floating error terminals by measuring finite impedances, a true floating error terminal judgment section that adds any one of a P channel-type transistor and an N channel-type transistor to terminals of the circuit where it is judged that there are floating error terminals and calculates changes in potential at the terminals and adds the other of the P channel-type transistor and the N channel-type transistor to the terminals and calculates changes in potential at the terminals, and an output section that outputs a judgment result of the floating error terminal judgment section and a judgment result of the true floating error terminal judgment section.

摘要翻译： 本发明的半导体集成电路的验证装置包括：提取电路网列表的电路网列表提取部，基于提取的网表执行电路模拟的电路模拟执行部，有限的 判断有无阻抗的存在或不存在的阻抗判定部，通过测量有限阻抗来判断浮动误差端子的存在或不存在的浮动误差终端判定部;真浮动误差终端判定部，将P沟道型晶体管 和N沟道型晶体管连接到电路的端子，其中判断出存在浮动误差端子并且计算端子处的电位变化，并将另一个P沟道型晶体管和N沟道型晶体管加到 终端，并计算终端的电位变化，以及输出判断输出部 浮动误差终端判断部分的结果和真实浮动错误终端判断部分的判断结果。

公开(公告)号：US20070206399A1

公开(公告)日：2007-09-06

申请号：US11682478

申请日：2007-03-06

申请人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

发明人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C16/0483 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/48227 ,  H01L2924/15311

摘要： A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a second area different from said first area of said semiconductor substrate, said first and second memory cell arrays being arranged in a first direction, and a first pad section for inputting data to and outputting data from said first memory cell array and said second memory cell array, said first pad section having a plurality of pads arranged between said first memory cell array and said second memory cell array along a second direction perpendicular to said first direction.

摘要翻译： 一种具有第一存储单元阵列的非易失性半导体存储器件，包括形成在半导体衬底的第一区域中的多个电重新编程和可擦除非易失性半导体存储单元，第二存储单元阵列包括多个电重编程和可擦除非易失性半导体存储单元 形成在与所述半导体衬底的所述第一区域不同的第二区域中，所述第一和第二存储单元阵列沿第一方向布置;以及第一焊盘区段，用于向所述第一存储单元阵列和所述第二存储单元阵列输入数据并输出数据 所述第一焊盘部分具有沿垂直于所述第一方向的第二方向布置在所述第一存储单元阵列和所述第二存储单元阵列之间的多个焊盘。

公开(公告)号：US07120078B2

公开(公告)日：2006-10-10

申请号：US10948818

申请日：2004-09-23

申请人： Kazuaki Kawaguchi ,  Shigeo Ohshima

发明人： Kazuaki Kawaguchi ,  Shigeo Ohshima

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/4076

摘要： In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.

公开(公告)号：US06990040B2

公开(公告)日：2006-01-24

申请号：US10930591

申请日：2004-08-31

申请人： Shigeo Ohshima ,  Hiroyuki Ohtake ,  Katsumi Abe

发明人： Shigeo Ohshima ,  Hiroyuki Ohtake ,  Katsumi Abe

IPC分类号： G11C8/00

CPC分类号： G11C7/1069 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4076 ,  G11C2207/107

摘要： An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.

摘要翻译： 用于锁存写入数据的输入数据寄存器被布置在存储器芯部分的存储单元阵列附近的位置。 输入数据寄存器布置在用于将数据写入存储单元的数据路径的上游侧。 将写入数据引脚的数据输入写入到下游侧的终端位置，经由数据输入缓冲器，串行/并行转换电路和写数据线被锁存在输入数据寄存器中。 锁存在输入数据寄存器中的数据在下一个写周期中通过DQ写驱动器，数据线对，I / O门和位线对写入存储单元。

公开(公告)号：US06885606B2

公开(公告)日：2005-04-26

申请号：US10353271

申请日：2003-01-28

申请人： Noriyasu Kumazaki ,  Shigeo Ohshima ,  Kazuaki Kawaguchi

发明人： Noriyasu Kumazaki ,  Shigeo Ohshima ,  Kazuaki Kawaguchi

IPC分类号： G01R31/30 ,  G01R31/28 ,  G01R31/3185 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C29/06 ,  G11C8/00

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C8/12

摘要： A synchronous semiconductor memory device includes a plurality of memory banks which read data from memory cells and write data into the memory cells, a command decoder circuit which receives a command, detects whether the command is a read command or a write command, and, when detecting a read command or a write command, outputs a first control signal that enables a read operation or a write operation in the plurality of memory banks, bank select circuits which activate a second control signal to activate each of the memory banks, and bank timer circuits which deactivate the activated second control signal and perform control in such a manner that the timing with which the second control signal is deactivated in a test mode differs from that in a normal mode.

摘要翻译： 同步半导体存储器件包括从存储器单元读取数据并将数据写入存储单元的多个存储器组，接收命令的命令解码器电路，检测该命令是读命令还是写命令，以及何时 检测读取命令或写入命令，输出启用多个存储体中的读取操作或写入操作的第一控制信号，激活第二控制信号的存储体选择电路以激活每个存储体，以及存储体定时器 电路，其使激活的第二控制信号去激活并执行控制，使得在测试模式中第二控制信号被去激活的定时与正常模式不同。

公开(公告)号：US06867993B2

公开(公告)日：2005-03-15

申请号：US09910603

申请日：2001-07-19

申请人： Shigeo Ohshima ,  Nobuo Watanabe

发明人： Shigeo Ohshima ,  Nobuo Watanabe

IPC分类号： G11C11/401 ,  G11C5/06 ,  G11C29/34

CPC分类号： G11C5/066 ,  H01L2224/4826

摘要： In the package, a semiconductor chip is accommodated. This semiconductor chip has n pads (n is a natural number). The package has n pins connected to n pads.

摘要翻译： 在封装中，容纳半导体芯片。 该半导体芯片具有n个焊盘（n是自然数）。 该封装有n个引脚连接到n个焊盘。

公开(公告)号：US06795370B2

公开(公告)日：2004-09-21

申请号：US10369945

申请日：2003-02-18

申请人： Shigeo Ohshima ,  Hiroyuki Ohtake ,  Katsumi Abe

发明人： Shigeo Ohshima ,  Hiroyuki Ohtake ,  Katsumi Abe

IPC分类号： G11C800

CPC分类号： G11C7/1069 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4076 ,  G11C2207/107

摘要： An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.

摘要翻译： 用于锁存写入数据的输入数据寄存器被布置在存储器芯部分的存储单元阵列附近的位置。 输入数据寄存器布置在用于将数据写入存储单元的数据路径的上游侧。 将写入数据引脚的数据输入写入到下游侧的终端位置，经由数据输入缓冲器，串行/并行转换电路和写数据线被锁存在输入数据寄存器中。 锁存在输入数据寄存器中的数据在下一个写周期中通过DQ写驱动器，数据线对，I / O门和位线对写入存储单元。

公开(公告)号：US06545941B2

公开(公告)日：2003-04-08

申请号：US09966664

申请日：2001-09-27

申请人： Koji Kato ,  Shigeo Ohshima

发明人： Koji Kato ,  Shigeo Ohshima

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A clock synchronous circuit is stopped or started in accordance with the situation. More specifically, the clock synchronous circuit is stopped when no synchronous clock is necessary or in modes, such as a standby mode, bank active mode, refresh mode, and write mode, other than a read mode. In the read mode, the clock synchronous circuit is operated because a synchronous clock is necessary to output data. In the read mode, the number of clocks, i.e., CL, required from the time a read command is input to the time data is actually output, is 3 or more, when restarting and preamble of the clock synchronous circuit are taken into consideration.

公开(公告)号：US06226204B1

公开(公告)日：2001-05-01

申请号：US09141450

申请日：1998-08-27

申请人： Kazuko Inuzuka ,  Katsushi Nagaba ,  Shigeo Ohshima

发明人： Kazuko Inuzuka ,  Katsushi Nagaba ,  Shigeo Ohshima

IPC分类号： G11C1604

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： The data output circuit in a clock synchronous DRAM comprises a first data transfer circuit to which the data read from a memory is input and which transfers the input data to the output side in synchronization with an internal clock, an equalizing circuit to which the output of the first data transfer circuit is input during a read operation by a burst operation and to which high-impedance data is input after the read operation, a second data transfer circuit connected to the equalizing circuit, and an output buffer to which the output of the second data transfer circuit is input. The second data transfer circuit transfers all the data to the output buffer in synchronization with an output clock. This eliminates the dependence of the data access time and data hold time on data item and/or cycle and facilitates the timing control of the output control signal.

摘要翻译： 时钟同步DRAM中的数据输出电路包括第一数据传输电路，从存储器读取的数据被输入到该第一数据传输电路，并且将输入数据与内部时钟同步地传送到输出端;均衡电路， 第一数据传送电路在读操作期间通过脉冲串操作输入，并且在读操作之后输入高阻数据，连接到均衡电路的第二数据传输电路和输出缓冲器 第二数据传输电路被输入。 第二数据传输电路与输出时钟同步地将所有数据传送到输出缓冲器。 这消除了数据访问时间和数据保持时间对数据项和/或周期的依赖性，并且便于输出控制信号的定时控制。

公开(公告)号：US6046955A

公开(公告)日：2000-04-04

申请号：US271468

申请日：1999-03-17

申请人： Yasuhiro Suematsu ,  Shigeo Ohshima

发明人： Yasuhiro Suematsu ,  Shigeo Ohshima

IPC分类号： G01R31/28 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C29/04 ,  G11C29/34 ,  G11C8/00

CPC分类号： G11C8/12

摘要： A synchronous dynamic random access memory has spare columns which can be tested before shipping. In the memory, a mode set register outputs a multibank write signal in the test mode. A CBS latch circuit generates not only a signal for selecting the spare column decoders in banks and in the test mode but also signals for selecting the column decoders. Write driving circuits write the data onto the column lines selected by the column decoders and onto the spare column lines selected by the spare column decoders.

摘要翻译： 同步动态随机存取存储器有备用列，可在发货前进行测试。 在存储器中，模式设置寄存器在测试模式下输出多存储器写入信号。 CBS锁存电路不仅产生用于在存储体和测试模式中选择备用列解码器的信号，而且还生成用于选择列解码器的信号。 写驱动电路将数据写入由列解码器选择的列线上，并将其写入由备用列解码器选择的备用列线上。