公开(公告)号：US07369690B2

公开(公告)日：2008-05-06

申请号：US10660750

申请日：2003-09-12

Applicant: In-Soo Joo ,  Joon-Hoo Choi ,  Sung-Hoon Yang ,  Beohm-Rock Choi

Inventor： In-Soo Joo ,  Joon-Hoo Choi ,  Sung-Hoon Yang ,  Beohm-Rock Choi

IPC: G06K9/00 ,  G05B19/00

CPC classification number: G06K9/00899 ,  G06K9/0002

Abstract: In a fingerprint recognition apparatus, a first recognition section is formed on a center portion of a transparent substrate and a second recognition section is formed on the transparent substrate adjacent to the first recognition section. The first recognition section recognizes an image pattern from an object making contact with the transparent substrate to generate a first recognition signal and the second recognition section senses a biological signal so as to check whether or not the first recognition signal is obtained from a human being. Accordingly, the fingerprint recognition apparatus may check that whether or not the object having the image pattern is obtained from a human being, thereby recognizing the image pattern with high accuracy and improving reliability thereof.

Abstract translation: 在指纹识别装置中，在透明基板的中央部形成有第一识别部，在与第一识别部相邻的透明基板上形成第二识别部。 第一识别部识别来自与透明基板接触的物体的图像图案，以产生第一识别信号，并且第二识别部分感测生物信号，以便检查是否从人获得第一识别信号。 因此，指纹识别装置可以检查是否从人获得具有图像图案的对象，从而以高精度识别图像图案并提高其可靠性。

公开(公告)号：US20080049181A1

公开(公告)日：2008-02-28

申请号：US11933398

申请日：2007-10-31

Applicant: Seon-Ah CHO ,  Ji-Won SOHN ,  Mee-Hye JUNG ,  Sung-Hoon YANG ,  Jin-Won PARK ,  Dong-Gi SEONG ,  Kang-Woo KIM

Inventor： Seon-Ah CHO ,  Ji-Won SOHN ,  Mee-Hye JUNG ,  Sung-Hoon YANG ,  Jin-Won PARK ,  Dong-Gi SEONG ,  Kang-Woo KIM

IPC: G02F1/1343

CPC classification number: G02F1/136213

Abstract: A panel assembly includes gate wires, data wires, a plurality of pixel electrodes, a liquid crystal layer, and a common electrode. The gate wires include a plurality of gate lines and a plurality of first storage electrode lines parallel to the gate lines. The data wires include a plurality of data lines crossing and insulated from the gate lines and a plurality of second storage electrode lines overlapping the first storage electrode lines and spaced apart from the data lines. The plurality of pixel electrodes are disposed on and insulated from the data wires. The liquid crystal layer is disposed on the pixel electrodes and includes liquid crystal molecules, and the common electrode is disposed on the liquid crystal layer. One of the plurality of first storage electrode lines and the plurality of second storage electrode lines has varying widths.

Abstract translation: 面板组件包括栅极线，数据线，多个像素电极，液晶层和公共电极。 栅极线包括多条栅极线和与栅极线平行的多条第一存储电极线。 数据线包括与栅极线交叉并绝缘的多条数据线和与第一存储电极线重叠并与数据线间隔开的多条第二存储电极线。 多个像素电极设置在数据线上并与数据线绝缘。 液晶层设置在像素电极上并且包括液晶分子，并且公共电极设置在液晶层上。 多个第一存储电极线和多个第二存储电极线中的一个具有变化的宽度。

公开(公告)号：US20070012919A1

公开(公告)日：2007-01-18

申请号：US11487090

申请日：2006-07-15

Applicant: Min-seok Oh ,  Byoung-june Kim ,  Sang-gab Kim ,  Sung-hoon Yang ,  Hong-kee Chin ,  Kunal Girotra

Inventor： Min-seok Oh ,  Byoung-june Kim ,  Sang-gab Kim ,  Sung-hoon Yang ,  Hong-kee Chin ,  Kunal Girotra

IPC: H01L29/04

CPC classification number: H01L29/78618 ,  H01L27/124 ,  H01L29/458 ,  H01L29/66757

Abstract: Provided are a thin film transistor (TFT) substrate and a method for manufacturing the same. The method comprises forming on a substrate a conductive layer, an impurity-doped silicon layer, and an intermediate layer, wherein the intermediate layer comprises intrinsic silicon; patterning the intermediate layer, the impurity-doped silicon layer, and the conductive layer to form a data line, a source electrode, a drain electrode, ohmic contact portions, and intermediate portions, wherein an ohmic contact portion and an intermediate portion are on the source electrode, and an ohmic contact portion and an intermediate portion are on the drain electrode; forming an intrinsic silicon layer on the substrate; and patterning the intrinsic silicon layer to form a semiconductor layer forming channel portion between the source electrode and the drain electrode, and a contact portion on the intermediate portion.

Abstract translation: 提供一种薄膜晶体管（TFT）基板及其制造方法。 该方法包括在衬底上形成导电层，杂质掺杂硅层和中间层，其中中间层包含本征硅; 图案化中间层，杂质掺杂硅层和导电层，以形成数据线，源电极，漏电极，欧姆接触部分和中间部分，其中欧姆接触部分和中间部分在 源电极和欧姆接触部分和中间部分在漏电极上; 在衬底上形成本征硅层; 以及图案化本征硅层以在源电极和漏极之间形成沟道部分的半导体层，以及在中间部分上形成接触部分。

公开(公告)号：US20070002198A1

公开(公告)日：2007-01-04

申请号：US11444954

申请日：2006-05-31

Applicant: Sung-Hoon Yang ,  Won-Suk Shin ,  Byoung-June Kim

Inventor： Sung-Hoon Yang ,  Won-Suk Shin ,  Byoung-June Kim

IPC: G02F1/136

CPC classification number: G02F1/136286 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L27/124 ,  H01L29/4908

Abstract: The present invention provides a thin film transistor array panel comprising a substrate; a gate line containing Ag formed on the substrate at a low temperature to prevent agglomeration, a first gate insulating layer formed on the gate line, a second gate insulating layer formed on the first gate insulating layer, a data line perpendicularly intersecting the gate line, and a thin film transistor connected to the gate line and the data line, and a manufacturing method thereof.

Abstract translation: 本发明提供一种薄膜晶体管阵列板，其包括基板; 在低温下形成在基板上的Ag以防止凝聚的栅极线，形成在栅极线上的第一栅极绝缘层，形成在第一栅极绝缘层上的第二栅极绝缘层，与栅极线垂直相交的数据线， 以及连接到栅极线和数据线的薄膜晶体管及其制造方法。

公开(公告)号：US06984594B2

公开(公告)日：2006-01-10

申请号：US10150480

申请日：2002-05-17

Applicant: Sung-Hoon Yang ,  Glenn A. Cerny ,  Kyuha Chung ,  Byung-Keun Hwang ,  Wan-Shick Hong

Inventor： Sung-Hoon Yang ,  Glenn A. Cerny ,  Kyuha Chung ,  Byung-Keun Hwang ,  Wan-Shick Hong

IPC: H01L21/31

CPC classification number: H01L21/02126 ,  C23C16/401 ,  G02F1/1362 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31633 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a process for vapor depositing alow dielectric insulating film, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device.

Abstract translation: 本发明涉及一种用于气相沉积低介电绝缘膜的方法，更具体地说涉及一种低介电绝缘膜的气相淀积工艺，可以显着提高蒸镀速度，同时保持低介电绝缘膜的性能，从而解决寄生 实现高开口率结构的电容问题，并且可以通过使用硅烷气体通过CVD或PECVD方法蒸镀绝缘膜时减少处理时间，从而形成用于半导体器件的保护膜。

公开(公告)号：US06933568B2

公开(公告)日：2005-08-23

申请号：US10150482

申请日：2002-05-17

Applicant: Sung-Hoon Yang ,  Wan-Shick Hong ,  Kwan-Wook Jung

Inventor： Sung-Hoon Yang ,  Wan-Shick Hong ,  Kwan-Wook Jung

IPC: G02F1/1368 ,  C23C16/30 ,  C23C16/42 ,  G02F1/1362 ,  H01L21/205 ,  H01L21/312 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786 ,  H01L51/56 ,  H01L27/01 ,  H01L29/76 ,  H01L31/0288 ,  H01L31/112

CPC classification number: G02F1/136227 ,  C23C16/30 ,  G02F2001/136222 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3244 ,  H01L29/458 ,  H01L29/4908 ,  H01L51/56

Abstract: The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of lowdielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.

Abstract translation: 本发明涉及一种用于气相沉积低介电绝缘膜的方法，使用该方法的薄膜晶体管及其制备方法，更具体地涉及一种能够显着改善气相沉积的低电绝缘膜的气相沉积方法 同时保持低介电绝缘膜的性能，从而解决了寄生电容问题，以实现高开口率结构，并且通过使用硅烷气体通过CVD或PECVD方法蒸镀绝缘膜时可以减少处理时间，以形成保护 薄膜用于半导体器件。 本发明还涉及使用该方法及其制备方法的薄膜晶体管。

公开(公告)号：US09224900B2

公开(公告)日：2015-12-29

申请号：US12899409

申请日：2010-10-06

Applicant: Ki-Hun Jeong ,  Sung-Hoon Yang ,  Kap-Soo Yoon ,  Kyung-Sook Jeon ,  Seung Mi Seo

Inventor： Ki-Hun Jeong ,  Sung-Hoon Yang ,  Kap-Soo Yoon ,  Kyung-Sook Jeon ,  Seung Mi Seo

IPC: H01L31/113 ,  G02F1/133

CPC classification number: H01L31/1136 ,  G02F1/13318 ,  G06F2203/04103

Abstract: A touch sensitive display device utilizing infrared ray sensing transistors. The transistors are configured, and comprise specified materials, to allow them to be formed with fewer photolithography processes, reducing cost and manufacturing time.

Abstract translation: 一种使用红外线感测晶体管的触敏显示装置。 晶体管被配置并且包括指定的材料，以允许它们用更少的光刻工艺形成，从而降低成本和制造时间。

公开(公告)号：US09214106B2

公开(公告)日：2015-12-15

申请号：US13529690

申请日：2012-06-21

Applicant: Sang Youn Han ,  Byung Seong Bae ,  Jun Ho Song ,  Sung Hoon Yang ,  Ho Sik Jeon

Inventor： Sang Youn Han ,  Byung Seong Bae ,  Jun Ho Song ,  Sung Hoon Yang ,  Ho Sik Jeon

IPC: G01N21/00 ,  G01J1/00 ,  G09G3/20

CPC classification number: G09G3/2092 ,  G09G2354/00 ,  G09G2360/142

Abstract: Provided are a photo sensor, a display device including the same, and a driving method thereof. The photo sensor includes: an amplifying element including an input terminal coupled to a scan line for receiving a scan signal, an output terminal configured to output a sensing signal, and a control terminal connected to a first node; a sensing capacitor connected with the first node; a photosensitive sensing element including a control terminal connected with a terminal of a first control signal, an output terminal connected with the first node, and an input terminal; and a reset element connected with the output terminal of the amplifying element and resetting the output terminal of the amplifying element to second voltage according to a reset control signal.

Abstract translation: 提供了一种光传感器，包括该传感器的显示装置及其驱动方法。 光传感器包括：放大元件，包括耦合到用于接收扫描信号的扫描线的输入端子，被配置为输出感测信号的输出端子和连接到第一节点的控制端子; 与第一节点连接的感测电容器; 感光元件，包括与第一控制信号的端子连接的控制端子，与第一节点连接的输出端子和输入端子; 以及与放大元件的输出端子连接的复位元件，并根据复位控制信号将放大元件的输出端子复位为第二电压。

公开(公告)号：US09142704B2

公开(公告)日：2015-09-22

申请号：US13540677

申请日：2012-07-03

Applicant: Suk Won Jung ,  Seung Mi Seo ,  Sung Hoon Yang

Inventor： Suk Won Jung ,  Seung Mi Seo ,  Sung Hoon Yang

IPC: G06F3/042 ,  G06F3/041 ,  H01L31/167 ,  G02F1/1333 ,  G02F1/133

CPC classification number: H01L31/167 ,  G02F1/13338 ,  G02F2001/13312 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/0421

Abstract: A photosensor includes a sensing switching element, a sensing element, and a reset switching element. The sensing switching element includes an output terminal connected to a sensing signal line, a control terminal connected to a first gate line, and an input terminal connected to the first node. The sensing element includes an output terminal connected to a first node, a control terminal connected a second gate line disposed next to the first gate line, and an input terminal connected to a source voltage line transmitting a source voltage. The sensing element senses light. The reset switching element includes an output terminal connected to the first node, a control terminal connected to the second gate line, and an input terminal connected to a driving voltage line transmitting a driving voltage.

Abstract translation: 光传感器包括感测开关元件，感测元件和复位开关元件。 感测开关元件包括连接到感测信号线的输出端子，连接到第一栅极线的控制端子和连接到第一节点的输入端子。 感测元件包括连接到第一节点的输出端子，连接在第一栅极线旁边的第二栅极线的控制端子以及连接到发送源极电压的源极电压线的输入端子。 传感元件感光。 复位开关元件包括连接到第一节点的输出端子，连接到第二栅极线的控制端子和连接到传输驱动电压的驱动电压线的输入端子。

公开(公告)号：US08947623B2

公开(公告)日：2015-02-03

申请号：US13410894

申请日：2012-03-02

Applicant: Hyang-Shik Kong ,  Sung Hoon Yang ,  Se Hwan Yu ,  Yong Hwan Shin ,  Su Mi Lee ,  Shin Il Choi

Inventor： Hyang-Shik Kong ,  Sung Hoon Yang ,  Se Hwan Yu ,  Yong Hwan Shin ,  Su Mi Lee ,  Shin Il Choi

IPC: G02F1/1337 ,  G02F1/13 ,  G02F1/1335 ,  G02F1/1343

CPC classification number: G02F1/13439 ,  G02F1/133528 ,  G02F2001/133548 ,  G02F2001/133565

Abstract: A manufacturing method of a liquid crystal display includes: forming an etch target layer including a conductive material on a first substrate; forming a first mask layer on the etch target layer; forming a block copolymer coating layer including a plurality of polymers on the first mask layer; processing the block copolymer coating layer to form a block copolymer pattern layer including first and second polymer blocks; removing one of the first or second polymer blocks to form a second mask pattern layer; etching the first mask layer by using the second mask pattern layer as an etching mask to form a first mask pattern layer; and etching the etch target layer by using the first mask pattern layer as an etching mask to form a first electrode. The first electrode includes a plurality of the first minute patterns extending in a predetermined direction and having a polarization function.