公开(公告)号：US07682910B2

公开(公告)日：2010-03-23

申请号：US12101323

申请日：2008-04-11

Applicant: Terence B. Hook ,  Gerald Leake, Jr.

Inventor： Terence B. Hook ,  Gerald Leake, Jr.

IPC: H01L21/8236 ,  H01L21/75 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/2652

Abstract: A first semiconductor region and a second semiconductor region separated by a shallow trench isolation region are formed in a semiconductor substrate. A photoresist is applied and patterned so that the first semiconductor region is exposed, while the second semiconductor region is covered. Depending on the setting of parameters for the location of an edge of the patterned photoresist, the slope of sidewalls of the photoresist, the thickness of the photoresist, and the direction of ion implantation, ions may, or may not, be implanted into the entirety of the surface portion of the first semiconductor region by shading or non-shading of the first semiconductor region. The semiconductor substrate may further comprise a third semiconductor region into which the dopants are implanted irrespective of the shading or non-shading of the first semiconductor region. The selection of shading or non-shading may be changed from substrate to substrate in manufacturing.

Abstract translation: 在半导体衬底中形成由浅沟槽隔离区隔开的第一半导体区域和第二半导体区域。 施加和图案化光致抗蚀剂，使得第一半导体区域被暴露，同时覆盖第二半导体区域。 取决于图案化光致抗蚀剂的边缘位置的参数的设置，光致抗蚀剂侧壁的斜率，光致抗蚀剂的厚度和离子注入的方向，离子可以或可以不植入整体 通过第一半导体区域的阴影或非阴影来形成第一半导体区域的表面部分。 半导体衬底还可以包括其中注入掺杂剂的第三半导体区域，而与第一半导体区域的阴影或非阴影无关。 阴影或非阴影的选择可以在制造过程中从衬底改变到衬底。

公开(公告)号：US20100025769A1

公开(公告)日：2010-02-04

申请号：US12185368

申请日：2008-08-04

Applicant: Terence B. Hook ,  Jenny Hu ,  Jaee-Eun Park

Inventor： Terence B. Hook ,  Jenny Hu ,  Jaee-Eun Park

IPC: H01L27/06 ,  H01L21/8238

CPC classification number: H01L27/0738 ,  H01L29/78

Abstract: The present invention provides a method of controlling bias in an electrical device including providing semiconductor devices on a bulk semiconductor substrate each including an active body region that is isolated from the active body region of adjacent devices, and providing a body resistor in electrical contact with the active body region of the bulk semiconductor substrate, wherein the body resistor provides for adjustability of the body potential of the semiconductor devices. In another aspect the present invention provides a semiconductor device including a bulk semiconductor substrate, at least one field effect transistor formed on the bulk semiconductor substrate including an isolated active body region, and a resistor in electrical communication with the isolated active body region.

Abstract translation: 本发明提供了一种控制电气装置中的偏置的方法，包括提供在体半导体衬底上的半导体器件，每个半导体器件包括与相邻器件的有源体区隔离的有源体区域，以及提供与电极接触的体电阻器 活体体区域，其中体电阻器提供半导体器件的体电位的可调节性。 在另一方面，本发明提供了一种半导体器件，其包括体半导体衬底，形成在包括隔离的有源体区域的体半导体衬底上的至少一个场效应晶体管和与隔离的有源体区域电连通的电阻器。

公开(公告)号：US07615827B2

公开(公告)日：2009-11-10

申请号：US11415787

申请日：2006-05-02

Applicant: Brent A. Anderson ,  Terence B. Hook

Inventor： Brent A. Anderson ,  Terence B. Hook

IPC: H01L29/72

CPC classification number: H01L21/823857

Abstract: Dual thickness devices and circuits using dual gate thickness devices. The devices include: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, the one or more FETs of the first polarity electrically connected to the one or more FETs of the second polarity in a same circuit, at least one of the one or more FETs of the first polarity having a gate dielectric consisting of a single layer of thermal silicon oxide and having a thickness different from a thickness of a gate dielectric consisting of a single layer of thermal silicon oxide of at least one of the one or more FETs of the second polarity.

Abstract translation: 双厚度器件和电路采用双栅极厚度器件。 这些器件包括：一个或多个第一极性的FET和一个或多个具有第二和相反极性的FET，所述第一极性的一个或多个FET在相同的电路中电连接到所述一个或多个第二极性的FET， 所述第一极性的所述一个或多个FET中的至少一个具有栅电介质，所述栅极电介质由单层热氧化硅组成，并且具有不同于至少由单层热氧化硅组成的栅极电介质的厚度的厚度 一个或多个第二极性的FET之一。

公开(公告)号：US07566946B2

公开(公告)日：2009-07-28

申请号：US11865432

申请日：2007-10-01

Applicant: Douglas D. Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

IPC: H01C10/00

CPC classification number: H01L27/0802 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.

Abstract translation: 在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。 多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个 具有高于目标值的值，并且具有低于目标值的值。 每个无源电路元件还具有与其串联的保险丝。 还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。 然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择 元素。

公开(公告)号：US20080157159A1

公开(公告)日：2008-07-03

申请号：US11617322

申请日：2006-12-28

Applicant: Terence B. Hook ,  Jae-Eun Park

Inventor： Terence B. Hook ,  Jae-Eun Park

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L29/945

Abstract: A metal-on-semiconductor varactor with a high value of Cmax/Cmin comprises a semiconductor bottom plate with an array of semiconductor pillars. The pillars may be in an accumulation mode to provide a high capacitance or in a depletion mode to provide a low capacitance. The maximum capacitance in an accumulation mode is primarily determined by the capacitance of the semiconductor pillars. The minimum capacitance in a depletion mode is primarily determined by a capacitor formed on an inter-pillar semiconductor surface between the semiconductor pillars. The minimum capacitance, and hence the value of Cmax/Cmin may be tuned by adjusting process parameters, design parameters and by alterations in the MOS varactor structure such as forming a highly doped semiconductor layer beneath the inter-pillar semiconductor surface or forming a plate insulator.

Abstract translation: 具有高值C max / C min以上的金属半导体变容二极管包括具有半导体柱阵列的半导体底板。 柱可以处于累积模式以提供高电容或耗尽模式以提供低电容。 累积模式下的最大电容主要由半导体支柱的电容决定。 耗尽模式中的最小电容主要由形成在半导体柱之间的柱间半导体表面上的电容器决定。 可以通过调整工艺参数，设计参数和通过MOS变容二极管结构中的改变来调整最小电容，并因此调整最小电容值，并因此调整最小电容值，例如形成 柱内半导体表面下方的高度掺杂的半导体层或形成板绝缘体。

公开(公告)号：US07173338B2

公开(公告)日：2007-02-06

申请号：US10708486

申请日：2004-03-06

Applicant: Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

Inventor： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

IPC: H01L23/48

CPC classification number: H01L21/7684 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

Abstract translation: 用于抑制半导体加工中的局部金属沉淀形成（LMPF）的方法和结构。 对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。 结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。 可以在金属线周围形成监测斜坡端子并与金属线电断开。 通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

公开(公告)号：US07132323B2

公开(公告)日：2006-11-07

申请号：US10713447

申请日：2003-11-14

Applicant: Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

Inventor： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

IPC: H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/823892 ,  H01L27/0928

Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

Abstract translation: 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

公开(公告)号：US07067886B2

公开(公告)日：2006-06-27

申请号：US10605888

申请日：2003-11-04

Applicant: Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

Inventor： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

IPC: H01L23/62

CPC classification number: H01L27/0251

Abstract: A method and structure alters an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

Abstract translation: 一种方法和结构改变具有硅绝缘体（SOI）晶体管的集成电路设计。 该方法/结构通过在集成电路设计中跟踪电网来防止在处理到SOI晶体管的栅极期间的充电损坏，识别在源极/漏极和栅极之间具有电压差的SOI晶体管作为潜在损坏的SOI晶体管（基于 跟踪电网），并且在每个潜在损坏的SOI晶体管的源极/漏极和栅极之间连接分流器件。 或者，方法/结构提供通过串联装置连接补偿导体。

公开(公告)号：US06956417B2

公开(公告)日：2005-10-18

申请号：US10707123

申请日：2003-11-21

Applicant: Kerry Bernstein ,  Anthony R. Bonaccio ,  John A. Fifield ,  Allen P. Haar ,  Shiu C. Ho ,  Terence B. Hook ,  Michael A. Soma ,  Stephen D. Wyatt

Inventor： Kerry Bernstein ,  Anthony R. Bonaccio ,  John A. Fifield ,  Allen P. Haar ,  Shiu C. Ho ,  Terence B. Hook ,  Michael A. Soma ,  Stephen D. Wyatt

IPC: H03L7/06 ,  H03L7/089 ,  H03L7/093

CPC classification number: H03L7/093 ,  H03L7/0891

Abstract: A circuit, including: a capacitor coupled between a first circuit node and a second circuit node and that leaks a leakage current from the first circuit node to the second circuit node; and a compensation circuit adapted to supply a compensatory current to compensate for the leakage current to the first circuit node.

Abstract translation: 一种电路，包括：电容器，耦合在第一电路节点和第二电路节点之间，并且泄漏电流从第一电路节点泄漏到第二电路节点; 以及补偿电路，其适于提供补偿电流以补偿到第一电路节点的漏电流。

公开(公告)号：US06825490B1

公开(公告)日：2004-11-30

申请号：US10605567

申请日：2003-10-09

Applicant: Terence B. Hook ,  Raminderpal Singh ,  Stephen D. Wyatt

Inventor： Terence B. Hook ,  Raminderpal Singh ,  Stephen D. Wyatt

IPC: H01L2358

CPC classification number: G01R35/005

Abstract: A structure and associated method to determine an actual resistance value of a calibration resistor within a semiconductor device. The semiconductor device comprises a capacitor, a calibration resistor, and a calibration circuit. A voltage applied to the calibration resistor produces a current flow through the calibration resistor to charge the capacitor. The calibration circuit is adapted to measure an actual time required to charge the capacitor. The calibration circuit is further adapted calculate an actual resistance value of the calibration resistor based on the actual time required to charge the capacitor and a capacitance value of the capacitor.

Abstract translation: 确定半导体器件内校准电阻器的实际电阻值的结构和相关方法。 半导体器件包括电容器，校准电阻器和校准电路。 施加到校准电阻器的电压产生通过校准电阻器的电流，以对电容器充电。 校准电路适于测量对电容器充电所需的实际时间。 校准电路还适用于根据电容器充电所需的实际时间和电容器的电容值来计算校准电阻器的实际电阻值。