Substrate Having a Coating Comprising Copper and Method for the Production Thereof by Means of Atomic Layer Deposition
    61.
    发明申请
    Substrate Having a Coating Comprising Copper and Method for the Production Thereof by Means of Atomic Layer Deposition 有权
    具有包含铜的涂层的基体及其通过原子层沉积法生产的方法

    公开(公告)号:US20100301478A1

    公开(公告)日:2010-12-02

    申请号:US12794454

    申请日:2010-06-04

    Abstract: A method can be used for the production of a coated substrate. The coating contains copper. A copper precursor and a substrate are provided. The copper precursor is a copper(I) complex which contains no fluorine. A copper-containing layer is deposited by means of atomic layer deposition (ALD) at least on partial regions of the substrate surface by using the precursor. Optionally, a reduction step is performed in which a reducing agent acts on the substrate obtained in the layer deposition step. In various embodiments, the precursor is a complex of the formula L2Cu(X∩X) in which L are identical or different σ-donor-π acceptor ligands and/or identical or different σ,π-donor-π acceptor ligands and X∩X is a bidentate ligand which is selected from the group consisting of β-diketonates, β-ketoiminates, β-diiminates, amidinates, carboxylates and thiocarboxylates.

    Abstract translation: 可以使用一种方法来生产涂覆的基底。 涂层含有铜。 提供铜前体和基底。 铜前体是不含氟的铜(I)络合物。 通过使用前体,通过原子层沉积(ALD)至少在衬底表面的部分区域上沉积含铜层。 任选地,进行还原步骤,其中还原剂作用在在层沉积步骤中获得的基底上。 在各种实施方案中,前体是式L2Cu(X∩X)的络合物,其中L是相同或不同的,并且被供体 - 受体配体和/或相同或不同的“和” - 供体 - 受体配体和X∩X是二齿配体,其选自& big-二酮化合物,酮基,β-二亚胺,脒基,羧酸酯和硫代羧酸盐。

    Use Of Phenothiazine-S-Oxides And Phenothiazine -S,S-Dioxides In The Form Of Matrix Materials For Organic Light-Emitting Diodes
    65.
    发明申请
    Use Of Phenothiazine-S-Oxides And Phenothiazine -S,S-Dioxides In The Form Of Matrix Materials For Organic Light-Emitting Diodes 审中-公开
    用于有机发光二极管的基质材料形式的吩噻嗪-S-氧化物和吩噻嗪-S,S-二氧化物

    公开(公告)号:US20080018238A1

    公开(公告)日:2008-01-24

    申请号:US11720156

    申请日:2005-11-23

    Abstract: The present invention relates to the use of phenothiazine S-oxides and S,S-dioxides as matrix materials for organic light-emitting diodes, in particular as matrix materials in the light-emitting layer of the organic light-emitting diodes, to organic light-emitting diodes comprising a light-emitting layer which comprises at least one phenothiazine S-oxide or S,S-dioxide as a matrix material and at least one further substance distributed therein as an emitter, to light-emitting layers which comprise at least one phenothiazine S-oxide or S,S-dioxide as a matrix material and at least one substance distributed therein as an emitter, to light-emitting layers which consist of one or more phenothiazine S-oxides or S,S-dioxides as a matrix material and at least one further substance distributed therein as a matrix material, to organic light-emitting diodes which comprise corresponding light-emitting layers, and to devices which comprise corresponding organic light-emitting diodes.

    Abstract translation: 本发明涉及吩噻嗪S-氧化物和S,S-二氧化物作为有机发光二极管的基质材料,特别是作为有机发光二极管的发光层中的基质材料的有机发光二极管的有机发光 包含发光层的发光二极管包括至少一种吩噻嗪S-氧化物或作为基质材料的S,S-二氧化物和分布在其中的至少一种其它物质作为发射体,发光层包括至少一个 吩噻嗪S-氧化物或作为基质材料的S,S-二氧化物和作为发射体分布在其中的至少一种物质发射到由一种或多种吩噻嗪S-氧化物或S,S-二氧化物组成的发光层作为基质材料 以及作为基质材料分布在其中的至少一种其它物质,包括对应的发光层的有机发光二极管以及包括相应的有机发光二极管的器件。

    Microstructure and method for the production thereof
    67.
    发明授权
    Microstructure and method for the production thereof 失效
    微结构及其制造方法

    公开(公告)号:US06969628B2

    公开(公告)日:2005-11-29

    申请号:US10296771

    申请日:2001-06-13

    CPC classification number: B81B3/0086 B81B2203/033 B81C2201/016

    Abstract: The invention relates to a microstructure in a preferably electrically conductive substrate (1), more specifically made of doped single crystal silicon, with at least one functional unit (2.1, 2.2) and to a method of fabricating the same. In accordance with the invention, the functional unit (2.1, 2.2) is mechanically and electrically separated from the substrate (1) on all sides by means of isolation gaps (5, 5a) and is connected, on at least one site, to a first structure (4a) of an electrically conductive layer (S) that is electrically isolated from the substrate (1) by way of an isolation layer (3) and that secures the unit into position relative to the substrate (1). For this purpose, the functional unit (2.1, 2.2) is released from the substrate (1) in such a manner that the isolation gaps (5, 5a) are provided on all sides relative to the substrate (1). The electrically conductive layer (S) is applied in such a manner that it is connected through contact fingers (4a) for example to the functional unit (2.1, 2.2) which it secures into position. The method in accordance with the invention permits to substantially facilitate the manufacturing process and to produce a microstructure with but small parasitic capacitances.

    Abstract translation: 本发明涉及在具有至少一个功能单元(2.1,2.2)的优选导电衬底(1)中,更具体地由掺杂单晶硅制成的微观结构及其制造方法。 根据本发明,通过隔离间隙(5,5a),功能单元(2.1,2.2)在所有侧面上与基板​​(1)机械地和电气地分开,并且在至少一个位置连接到 通过隔离层(3)与衬底(1)电绝缘的导电层(S)的第一结构(4a),并且将单元固定在相对于衬底(1)的位置。 为此,功能单元(2.1,2.2)以这样的方式从基板(1)释放,使得隔离间隙(5,5a)相对于基板(1)设置在所有侧面上。 导电层(S)以这样的方式被施加,使得它通过接触指状物(4a)例如连接到功能单元(2.1,2.2)上,其被固定到位。 根据本发明的方法允许基本上方便制造过程并产生具有小的寄生电容的微结构。

    Vertical transistor comprising a mobile gate and a method for the production thereof
    68.
    发明授权
    Vertical transistor comprising a mobile gate and a method for the production thereof 失效
    包括移动门的垂直晶体管及其制造方法

    公开(公告)号:US06849912B2

    公开(公告)日:2005-02-01

    申请号:US10311759

    申请日:2001-04-26

    CPC classification number: H01L29/84 G01L9/0098 G01P15/0802 G01P15/124

    Abstract: What is proposed is a vertical field effect transistor produced from a semiconductor wafer, comprising a residual transistor composed of a source zone, a channel zone and a drain zone, as well as a movable gate structure disposed by means of at least one flexible suspension in front of said channel zone and spaced therefrom, which is characterized by the provision that the movable gate structure consists of the material of said semiconductor wafer. The suspensions of the movable structure preferably present a high ratio of their height to their width, such that the movable gate may preferably move in the wafer plane.

    Abstract translation: 提出的是由半导体晶片制造的垂直场效应晶体管,其包括由源极区,沟道区和漏极区组成的残余晶体管,以及通过至少一个柔性悬浮体设置的可移动栅极结构 所述通道区域的前部并与其间隔开,其特征在于,所述可移动栅极结构由所述半导体晶片的材料构成。 可移动结构的悬架优选地将其高度与其宽度的高比率呈现,使得可移动门优选地在晶片平面中移动。

    Micromechanical accelerometer with plate-like semiconductor wafers
    69.
    发明授权
    Micromechanical accelerometer with plate-like semiconductor wafers 失效
    具有板状半导体晶片的微机械加速度计

    公开(公告)号:US5614742A

    公开(公告)日:1997-03-25

    申请号:US587604

    申请日:1996-01-02

    Abstract: A high precision micromechanical accelerometer comprises a layered structure of five (5) semiconductor wafers insulated from one another by thin oxide layers. The accelerometer is formed by first connecting a coverplate and a baseplate to associated insulating plates. Counter-electrodes, produced by anisotropic etching from the respective insulating plates, are fixed to the coverplate and the baseplate respectively. The counter-electrodes are contactable through the cover or baseplate via contact windows. A central wafer contains a unilaterally linked mass (pendulum) that is also produced by anisotropic etching and which serves as a movable central electrode of a differential capacitor. The layered structure is hermetically sealed by semiconductor fusion bonding. A stepped gradation from the top is formed at a wafer edge region for attaching contact pads to individual wafers to permit electrical contacting of individual wafers. The invention permits fabrication of a .mu.B device characterized by extremely small leakage capacitances and high temperature stability.

    Abstract translation: 高精度微机械加速度计包括由半氧化物层彼此绝缘的五(5)个半导体晶片的分层结构。 通过首先将盖板和底板连接到相关联的绝缘板来形成加速度计。 通过各自绝缘板的各向异性蚀刻制成的对电极分别固定在盖板和底板上。 相对电极可以通过接触窗口通过盖板或底板接触。 中央晶片包含单向连接的质量(摆),其也通过各向异性蚀刻产生,并且用作差分电容器的可移动中心电极。 层状结构通过半导体熔融粘合而密封。 在晶片边缘区域形成从顶部的阶梯状梯度,用于将接触焊盘附接到单个晶片以允许单个晶片的电接触。 本发明允许制造以极小的泄漏电容和高温稳定性为特征的μB器件。

    Micromechanical accelerometer and method of manufacture thereof
    70.
    发明授权
    Micromechanical accelerometer and method of manufacture thereof 失效
    微机械加速度计及其制造方法

    公开(公告)号:US5504032A

    公开(公告)日:1996-04-02

    申请号:US224750

    申请日:1994-04-07

    Abstract: A high precision micromechanical accelerometer comprises a layered structure of five (5) semiconductor wafers insulated from one another by thin semiconductor material oxide layers. The accelerometer is formed by first connecting a coverplate and a baseplate to associated insulating plates. Counter-electrodes, produced by anisotropic etching from the respective insulating plates, are fixed to the coverplate and the baseplate respectively. The counter-electrodes are contactable through the cover or baseplate via contact windows. A central wafer contains a unilaterally linked mass (pendulum) that is also produced by anisotropic etching and which serves as a movable central electrode of a differential capacitor. The layered structure is hermetically sealed by semiconductor fusion bonding. A stepped gradation from the top is formed at a wafer edge region for attaching contact pads to individual wafers to permit electrical contacting of individual wafers. The invention permits fabrication of a .mu.B device characterized by extremely small leakage capacitances and high temperature stability.

    Abstract translation: 一种高精度微机械加速度计包括由薄半导体材料氧化物层彼此绝缘的五(5)个半导体晶片的分层结构。 通过首先将盖板和底板连接到相关联的绝缘板来形成加速度计。 通过各自绝缘板的各向异性蚀刻制成的对电极分别固定在盖板和基板上。 相对电极可以通过接触窗口通过盖板或底板接触。 中央晶片包含单向连接的质量(摆),其也通过各向异性蚀刻产生,并且用作差分电容器的可移动中心电极。 层状结构通过半导体熔融粘合而密封。 在晶片边缘区域形成从顶部的阶梯状梯度,用于将接触焊盘附接到单个晶片以允许单个晶片的电接触。 本发明允许制造以极小的泄漏电容和高温稳定性为特征的μB器件。

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