公开(公告)号：US20100002506A1

公开(公告)日：2010-01-07

申请号：US12318560

申请日：2008-12-31

Applicant: Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Yong June Kim

Inventor： Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Yong June Kim

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G11C29/00 ,  G11C2211/5621

Abstract: Provided are memory devices and memory programming methods. A memory device may include: a multi-level cell array that includes a plurality of multi-level cells; a programming unit that programs a first data page in the plurality of multi-level cells and programs a second data page in a multi-level cell from among the plurality of multi-level cells in which the first data page is programmed; an error analysis unit that analyzes read error information corresponding to the first data page based on a read voltage level to determine whether to correct a read error based on the analyzed read error information; and a controller that adjusts the read voltage level of the first data page depending on the determination result. Through this, it is possible to reduce an error occurrence when reading and/or programming a data page.

Abstract translation: 提供的是存储器件和存储器编程方法。 存储器件可以包括：多级单元阵列，其包括多个多电平单元; 编程单元，其对所述多个多电平单元中的第一数据页进行编程，并从所述第一数据页被编程的所述多个多电平单元中编程多电平单元中的第二数据页; 误差分析单元，其基于读取电压电平分析与所述第一数据页相对应的读取错误信息，以基于所分析的读取错误信息来确定是否校正读取错误; 以及控制器，其根据确定结果调整第一数据页的读取电压电平。 通过这种方式，可以在读取和/或编程数据页时减少错误发生。

公开(公告)号：US20090285023A1

公开(公告)日：2009-11-19

申请号：US12453108

申请日：2009-04-29

Applicant: Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

Inventor： Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

IPC: G11C16/02 ,  G11C7/00 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

Abstract: Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.

Abstract translation: 提供的是存储器件和存储器编程方法。 存储器件可以包括包括多个多位单元的多位单元阵列，编程单元，被配置为对多个多位单元中的第一数据页进行编程，并编程多位单元中的第二数据页 具有编程的第一数据页的单元，被配置为将多位单元与编程的第一数据页划分为第一组和第二组的第一控制器，以及配置成将每个的第一数据页的目标阈值电压间隔 基于第一读取电压电平和第二数据页面包括在第一组中的多位单元，并且基于第二读取阈值电压电平来设置包括在第二组中的每个多位单元的目标阈值电压间隔，以及 第二个数据页面。

公开(公告)号：US20090282319A1

公开(公告)日：2009-11-12

申请号：US12428511

申请日：2009-04-23

Applicant: Jong Seon No ,  Beom Kyu Shin ,  Seok Il Youn ,  Jae Dong Yang ,  Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Kyoung Lae Cho

Inventor： Jong Seon No ,  Beom Kyu Shin ,  Seok Il Youn ,  Jae Dong Yang ,  Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Kyoung Lae Cho

IPC: H03M13/15 ,  G06F11/10 ,  H03M13/45

CPC classification number: H03M13/2906 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/1194 ,  H03M13/136 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/296 ,  H03M13/3707 ,  H03M13/3738

Abstract: A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.

Abstract translation: 解码器包括多个解码器级和控制器。 解码器级使用相应的不同解码算法对接收到的信号执行解码操作。 控制器确定解码器中的一个相对于接收信号执行的解码操作是否成功，并且响应于确定的结果来控制每个其他解码器级的解码操作。

公开(公告)号：US20090234792A1

公开(公告)日：2009-09-17

申请号：US12292539

申请日：2008-11-20

Applicant: Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

Inventor： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

IPC: G06N5/00

CPC classification number: G06N99/005

Abstract: Disclosed are a memory device and a data decision method. The memory device may include a memory cell array, and a decision unit configured to read first data from the memory cell array via a first channel, perform at least one of a hard and soft decision on the first data using a first number of decision levels set based on characteristics of the first channel, read second data from the memory cell array via a second channel, and perform a soft decision on the second data using a second number of decision levels set based on characteristics of the second channel.

Abstract translation: 公开了一种存储器件和数据判定方法。 存储器装置可以包括存储单元阵列，以及判定单元，被配置为经由第一通道从存储单元阵列读取第一数据，使用第一数量的判定级别对第一数据执行硬判决和软判决中的至少一个 基于第一信道的特性设置，经由第二信道从存储器单元阵列读取第二数据，并且使用基于第二信道的特性设置的第二数量的判定级来对第二数据执行软判决。

公开(公告)号：US07590914B2

公开(公告)日：2009-09-15

申请号：US11105922

申请日：2005-04-13

Applicant: Sunghwan Kim ,  Yong-June Kim ,  Jong-Seon No ,  Sang-Hyun Lee ,  Yun-Hee Kim ,  Jae-Young Ahn

Inventor： Sunghwan Kim ,  Yong-June Kim ,  Jong-Seon No ,  Sang-Hyun Lee ,  Yun-Hee Kim ,  Jae-Young Ahn

IPC: H03M13/00

CPC classification number: H03M13/6356 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/6362

Abstract: Disclosed is a decoding apparatus for LDPC (Low-Density Parity-Check) codes when receiving data encoded with LDPC codes on a channel having consecutive output values, and a method thereof. The decoding method for LDPC codes uses sequential decoding and includes the following steps: (a) the nodes are divided according to a parity-check matrix into check nodes for a parity-check message and variable nodes for a bit message; (b) the check nodes are divided into a predetermined number of subsets; (c) the LDPC codeword of each subset for all the check nodes is sequentially decoded; (d) an output message is generated for verifying validity of the decoding result; and (e) the steps (b), (c), and (d) are iteratively performed by a predetermined number of iterations.

Abstract translation: 公开了一种在具有连续输出值的信道上接收用LDPC码编码的数据时的LDPC（低密度奇偶校验）码的解码装置及其方法。 LDPC码的解码方法使用顺序解码，包括以下步骤：（a）根据奇偶校验矩阵将节点划分成用于奇偶校验消息的校验节点和位消息的可变节点; （b）校验节点被划分成预定数量的子集; （c）所有校验节点的每个子集的LDPC码字被顺序解码; （d）生成用于验证解码结果的有效性的输出消息; 和（e）通过预定次数的迭代迭代地执行步骤（b），（c）和（d）。

公开(公告)号：US08806302B2

公开(公告)日：2014-08-12

申请号：US12654578

申请日：2009-12-23

Applicant: Yong June Kim ,  Junjin Kong ,  Jaehong Kim ,  Hong Rak Son

Inventor： Yong June Kim ,  Junjin Kong ,  Jaehong Kim ,  Hong Rak Son

IPC: G11C29/00

CPC classification number: G11C13/00 ,  G11C7/1006 ,  G11C11/5628 ,  G11C13/0033 ,  G11C16/3427 ,  G11C29/00

Abstract: Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states.

Abstract translation: 提供了一种半导体存储器件中的数据处理方法。 数据处理方法按行或列方向排列要编程在非易失性存储器件的行和列中的数据。 数据处理方法将编程数据编码成行或列方向的调制码，使得非易失性存储器件的相邻存储单元对被阻止被编程到第一和第二状态。

公开(公告)号：US08782490B2

公开(公告)日：2014-07-15

申请号：US13103460

申请日：2011-05-09

Applicant: Yong June Kim ,  Kyoung Lae Cho ,  Hong Rak Son

Inventor： Yong June Kim ,  Kyoung Lae Cho ,  Hong Rak Son

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/10 ,  G11C29/04 ,  H03M7/46

CPC classification number: G06F11/1048 ,  G11C29/10 ,  G11C2029/0411 ,  H03M7/46

Abstract: A data storage device includes a non-volatile memory device including a plurality of memory cells and a memory controller. The memory controller is configured to modify an arrangement of program data and to program the modified program data into the plurality of memory cells. The memory controller modifies the program data to eliminate a given data pattern causing physical interference between adjacent memory cells from the modified program data.

Abstract translation: 数据存储装置包括包括多个存储器单元和存储器控制器的非易失性存储器件。 存储器控制器被配置为修改程序数据的布置并且将修改的程序数据编程到多个存储器单元中。 存储器控制器修改程序数据以消除给定的数据模式，从修改的程序数据导致相邻存储器单元之间的物理干扰。

公开(公告)号：US08607118B2

公开(公告)日：2013-12-10

申请号：US12475640

申请日：2009-06-01

Applicant: Jong Seon No ,  Beom Kyu Shin ,  Seok Il Youn ,  Jae Dong Yang ,  Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Kyoung Lae Cho

Inventor： Jong Seon No ,  Beom Kyu Shin ,  Seok Il Youn ,  Jae Dong Yang ,  Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Kyoung Lae Cho

IPC: H03M13/00

CPC classification number: H03M13/1105 ,  H03M13/136 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/3738 ,  H03M13/3753 ,  H04L1/0051 ,  H04L1/0057

Abstract: An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.

Abstract translation: 公开了一种迭代解码方法，并且包括相对于奇偶校验方程顺序执行多个迭代解码周期，直到奇偶校验方程被解析为止，或者在迭代次数的执行期间达到迭代解码周期的最大数量N 解码周期，在数据缓冲器中存储对应于最小数量的位错误的一组可变节点的最小估计值，并且当迭代解码周期数达到时，输出存储在数据缓冲器中的最小估计值作为最终解码结果 N.

公开(公告)号：US08482977B2

公开(公告)日：2013-07-09

申请号：US13039004

申请日：2011-03-02

Applicant: Yong June Kim ,  Jaehong Kim ,  Junjin Kong ,  Hong Rak Son

Inventor： Yong June Kim ,  Jaehong Kim ,  Junjin Kong ,  Hong Rak Son

IPC: G11C16/04

CPC classification number: G11C16/04

Abstract: A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits.

Abstract translation: 存储器件包括多个多位存储器单元。 根据纠错码对多个输入数据位进行编码，以产生包括多个位组的码字。 多个多位存储器单元中的相应的多位存储器单元被编程为表示码字的位组中的相应的一组。 码字的比特组可以是连续比特的组。 在一些实施例中，多位存储器单元被配置为以比特存储，并且码字的长度是m的整数倍。 可以从页单元或单元单元中的多位存储单元读取数据以恢复码字，并且可以根据纠错码对恢复的码字进行解码以恢复输入数据位。

公开(公告)号：US08397116B2

公开(公告)日：2013-03-12

申请号：US12652768

申请日：2010-01-06

Applicant: Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

Inventor： Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

IPC: H03M13/00

CPC classification number: H03M13/1111 ,  H03M13/1108 ,  H03M13/3707 ,  H03M13/451 ,  H03M13/458 ,  H04L1/0045 ,  H04L1/0057

Abstract: A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful.

Abstract translation: 解码方法包括当解码第一解码方法失败时执行第一解码方法并执行第二解码方法。 第一解码方法包括使用接收数据的概率值来更新多个可变节点和多个校验节点。 第二解码方法包括从多个可变节点中选择至少一个变量节点; 校正在所选择的至少一个可变节点中接收的数据的概率值; 使用校正的概率值更新变量节点和校验节点; 以及确定所述第二解码方法的解码是否成功。