公开(公告)号：US07759727B2

公开(公告)日：2010-07-20

申请号：US11639658

申请日：2006-12-14

申请人： Alexander Kalnitsky ,  John M. Caruso

发明人： Alexander Kalnitsky ,  John M. Caruso

IPC分类号： G11C16/04

CPC分类号： G11C27/005 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883

摘要： A method and corresponding structure for shielding a floating gate tunneling element. The method comprises disposing a floating gate over a gate oxide using standard CMOS processing in two active areas defined by first and second doped well regions formed in a substrate surrounded by field oxide, and forming a floating gate shield layer so as to enclose the floating gate. The floating gate includes a first floating gate portion over an active area in the first doped well region and a second floating gate portion over the active area in the second doped well region. The first floating gate portion is substantially smaller than the second floating gate portion so as to enable adequate voltage coupling for Fowler-Nordheim tunneling to occur between the first doped well region and the first floating gate portion. The direction of tunneling is determined by high voltage application to one of the doped well regions.

摘要翻译： 一种用于屏蔽浮动栅极隧道元件的方法和相应的结构。 该方法包括使用在由场氧化物包围的衬底中形成的第一和第二掺杂阱区域限定的两个有源区域中的标准CMOS处理在栅极氧化物上设置浮置栅极，以及形成浮置栅极屏蔽层以便包围浮置栅极 。 浮置栅极包括在第一掺杂阱区域中的有源区域上的第一浮动栅极部分和位于第二掺杂阱区域中的有源区域上的第二浮动栅极部分。 第一浮栅部分基本上小于第二浮栅部分，以便能够在第一掺杂阱区域和第一浮栅部分之间产生用于Fowler-Nordheim隧道的足够的电压耦合。 通过高压施加到掺杂阱区之一来确定隧道的方向。

公开(公告)号：US07755117B2

公开(公告)日：2010-07-13

申请号：US11621443

申请日：2007-01-09

申请人： Alexander Kalnitsky ,  Dong Zheng ,  Joy Jones ,  Xijian Lin ,  Gregory Cestra

发明人： Alexander Kalnitsky ,  Dong Zheng ,  Joy Jones ,  Xijian Lin ,  Gregory Cestra

IPC分类号： H01L31/062

CPC分类号： H01L31/103 ,  H01L27/1443 ,  H01L31/02162

摘要： Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors.

摘要翻译： 本发明的实施例涉及在抑制红外光的同时主要响应于可见光的光传感器。 这种传感器作为环境光传感器是特别有用的，因为这样的传感器可用于提供类似于人眼的光谱响应。 本发明的实施例还涉及提供这种光传感器的方法，以及使用这种光传感器的方法。

公开(公告)号：US20080296721A1

公开(公告)日：2008-12-04

申请号：US11849565

申请日：2007-09-04

申请人： Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

发明人： Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

IPC分类号： H01L29/47 ,  H01L21/28

CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L29/456 ,  H01L29/47 ,  H01L29/7833

摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

摘要翻译： 包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。 第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。 与第一硅化物不同的第二硅化物层位于阳极区上。 对阳极区域和阱的第二硅化物进行欧姆接触。

公开(公告)号：US20080266958A1

公开(公告)日：2008-10-30

申请号：US11861102

申请日：2007-09-25

申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

IPC分类号： G11C16/04

CPC分类号： G11C16/0416

摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

摘要翻译： 闪存阵列包括以行和列的矩阵组织的多个存储单元。 每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。 多个字线各自电连接到相应行中的每个存储器单元中的电容器。 第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。 多个高压存取晶体管分别电连接到第一组位线中的位线。 第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。 在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

公开(公告)号：US20070072326A1

公开(公告)日：2007-03-29

申请号：US11532762

申请日：2006-09-18

申请人： Dong Zheng ,  Phillip Benzel ,  Joy Jones ,  Alexander Kalnitsky ,  Perumal Ratman

发明人： Dong Zheng ,  Phillip Benzel ,  Joy Jones ,  Alexander Kalnitsky ,  Perumal Ratman

IPC分类号： H01L21/00 ,  H01L31/113 ,  H01L31/0203 ,  H01L31/062

CPC分类号： H01L27/1462 ,  H01L27/1463 ,  H01L31/02165

摘要： A method of a fabricating a multiple wavelength adapted photodiode and resulting photodiode includes the steps of providing a substrate having a first semiconductor type surface region on at least a portion thereof, implanting and forming a second semiconductor type shallow surface layer into the surface region, and forming a multi-layer anti-reflective coating (ARC) on the shallow surface layer. The forming step includes depositing or forming a thin oxide layer on the shallow surface layer and depositing a second dielectric layer different from the thin oxide layer on the thin oxide layer. An etch stop is formed on the second dielectric, wherein the etch stop includes at least one layer resistant to oxide etch. At least one oxide including layer (e.g. ILD) is then deposited on the etch stop. The oxide including layer and etch stop are then removed to expose at least a portion of the ARC to the ambient.

摘要翻译： 一种制造多波长适应光电二极管和所得光电二极管的方法包括以下步骤：在其至少一部分上提供具有第一半导体类型表面区域的衬底，将表面区域中的第二半导体型浅表面层注入并形成，以及 在浅表面层上形成多层抗反射涂层（ARC）。 形成步骤包括在浅表面层上沉积或形成薄氧化物层，并在薄氧化物层上沉积不同于薄氧化物层的第二电介质层。 蚀刻停止件形成在第二电介质上，其中蚀刻停止层包括至少一层抵抗氧化物蚀刻的层。 然后将至少一种包括层（例如ILD）的氧化物沉积在蚀刻停止件上。 然后去除包括氧化物层和蚀刻停止层，以将ARC的至少一部分暴露于环境中。

公开(公告)号：US07026666B2

公开(公告)日：2006-04-11

申请号：US10734928

申请日：2003-12-12

申请人： Alexander Kalnitsky ,  Alexel Shatalov ,  Michael Rowlandson ,  Sang H. Park ,  Robert F. Scheer ,  Fanling H. Yang

发明人： Alexander Kalnitsky ,  Alexel Shatalov ,  Michael Rowlandson ,  Sang H. Park ,  Robert F. Scheer ,  Fanling H. Yang

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/7378

摘要： A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first and second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.

公开(公告)号：US06767798B2

公开(公告)日：2004-07-27

申请号：US10119594

申请日：2002-04-09

申请人： Alexander Kalnitsky ,  Alexei Shatalov ,  Michael Rowlandson ,  Sang H. Park ,  Robert F. Scheer ,  Fanling H. Yang

发明人： Alexander Kalnitsky ,  Alexei Shatalov ,  Michael Rowlandson ,  Sang H. Park ,  Robert F. Scheer ,  Fanling H. Yang

IPC分类号： H01L21331

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/7378

摘要： A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first and second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.

摘要翻译： 提供自对准双极晶体管及其形成方法。 双极晶体管具有凸起的外在基极，使得通过提供比本征基底更厚的外在基极来降低连接基极电阻。 外部基极的厚度的增加提供了重掺杂基极区域的较小电阻层。 形成双极晶体管的方法包括在衬底上沉积第一外延层以形成具有本征基极区域和非本征基极区域的基极区域。 通过在第一外延层的一部分上沉积第二外延层使外部基极层的厚度为x，并且本征层的厚度为y，其中x> y，凸起外部基极区域。 使用化学气相外延装置沉积第二外延层，其中Ge至Si的浓度在外延过程中从高于5％逐渐降低至接近0％。 因此，第二外延层在第一和第二外延层的界面附近具有最高的Ge浓度。 在第二外延区域的顶面，Ge的浓度逐渐降低到接近0％。

公开(公告)号：US06531783B1

公开(公告)日：2003-03-11

申请号：US08436133

申请日：1995-05-08

申请人： Alexander Kalnitsky

发明人： Alexander Kalnitsky

IPC分类号： H01L2940

CPC分类号： H01L21/76802 ,  H01L21/31111 ,  Y10S438/97

摘要： A method is provided for depositing a silicon nitride layer to protect and isolate underlying layers during wet etching. The silicon nitride layer maintains the integrity of interconnect leads, bond pads, and die boundaries by acting as a wet etch stop. The silicon nitride layer stops the chemicals used in a wet etch from reaching underlying layers in the integrated circuit.

摘要翻译： 提供了一种沉积氮化硅层以在湿蚀刻期间保护和分离下层的方法。 氮化硅层通过充当湿蚀刻停止来保持互连引线，接合焊盘和管芯边界的完整性。 氮化硅层阻止在湿蚀刻中使用的化学品到达集成电路中的下层。

公开(公告)号：US06492237B2

公开(公告)日：2002-12-10

申请号：US09782820

申请日：2001-02-12

申请人： Alexander Kalnitsky ,  Sang Hoon Park ,  Robert F. Scheer

发明人： Alexander Kalnitsky ,  Sang Hoon Park ,  Robert F. Scheer

IPC分类号： H01L21331

CPC分类号： H01L29/66287

摘要： A method of forming an NPN semiconductor device includes the steps of forming a collector region within a substrate, forming a base region over the collector region, and forming an oxide-nitride-oxide stack over the base region. Once these three structures are formed, an opening is created through the oxide-nitride-oxide stack to expose the top surface of the base region. Then, a doped polysilicon material is used to fill the opening and make electrical contact to the base region. The use of the oxide-nitride-oxide stack with appropriate etching of the opening eliminates the exposure of the base region to reactive ion etch environment typical of prior art methods for forming NPN semiconductor devices. As an option, after the opening of the oxide-nitride-oxide stack is formed, a local oxidation of silicon (LOCOS) and etched can be preformed to create oxide spacers to line the opening wall above the base region.

摘要翻译： 形成NPN半导体器件的方法包括以下步骤：在衬底内形成集电极区域，在集电极区域上形成基极区域，并在基极区域上形成氧化物 - 氮化物 - 氧化物堆叠体。 一旦形成这三个结构，就通过氧化物 - 氧化物 - 氧化物堆叠形成一个开口，露出基极区域的顶面。 然后，使用掺杂多晶硅材料来填充开口并与基极区域电接触。 通过对开口的适当蚀刻来使用氧化物 - 氮化物 - 氧化物堆叠消除了基底区域对用于形成NPN半导体器件的现有技术方法的典型的反应离子蚀刻环境的曝光。 作为选择，在形成氧化物 - 氮化物 - 氧化物堆叠的打开之后，可以预先形成硅（LOCOS）的局部氧化并蚀刻以形成氧化物间隔物以使基部区域上方的开口壁成线。

公开(公告)号：US06384398B1

公开(公告)日：2002-05-07

申请号：US09851203

申请日：2001-05-08

申请人： Alexander Kalnitsky ,  Albert Bergemont ,  Pavel Poplevine

发明人： Alexander Kalnitsky ,  Albert Bergemont ,  Pavel Poplevine

IPC分类号： H01L2700

CPC分类号： H01L27/14654 ,  H01L27/14609 ,  H01L27/1463

摘要： The potential on a pixel cell having a gated diode and a read out transistor is set to an initial level prior to an image integration period. During the image integration period, absorbed photons cause the potential on the pixel cell to change. After the image integration period, the pixel cell is then reset and read out by applying a number of pulses to the gated diode. Each of the pulses causes a fixed amount of charge to be injected into the cell. When the potential on the cell has again returned to the initial level, the number of absorbed photons is determined by counting the number of pulses that were required to return the potential to the initial level. The read out transistor is used to determine when the potential is at the initial level by biasing the transistor to output a current that corresponds to the potential on the pixel cell.