公开(公告)号：US10402252B1

公开(公告)日：2019-09-03

申请号：US15085963

申请日：2016-03-30

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Eric Jason Brandwine

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F11/22

Abstract: A peripheral device may implement alternative reporting of errors and other events detected at the peripheral device. A peripheral device may monitor the operations of the peripheral device for reporting events. Upon detecting a reporting event, a notification of the reporting event may be generated and sent to a remote data store. The remote data store may store the reporting event and evaluate the reporting event for a responsive action that may be performed. If a responsive action is determined, then the remote data store may direct the performance of the responsive action. The remote data store may provide access to stored reporting events for a peripheral device.

公开(公告)号：US10346342B1

公开(公告)日：2019-07-09

申请号：US15451982

申请日：2017-03-07

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Thomas A. Volpe ,  Nafea Bshara ,  Yaniv Shapira ,  Adi Habusha

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40

Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.

公开(公告)号：US10268612B1

公开(公告)日：2019-04-23

申请号：US15275168

申请日：2016-09-23

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Mark Bradley Davis ,  Matthew Shawn Wilson ,  Uwe Dannowski ,  Yaniv Shapira ,  Adi Habusha ,  Anthony Nicholas Liguori

IPC: G06F13/30 ,  G06F13/40 ,  G06F3/06 ,  G06F12/0891 ,  G06F13/28

Abstract: Disclosed herein are techniques for migrating data from a source memory range to a destination memory while data is being written into the source memory range. An apparatus includes a control logic configured to receive a request for data migration and initiate the data migration using a direct memory access (DMA) controller, while the source memory range continues to accept write operations. The apparatus also includes a tracking logic coupled to the control logic and configured to track write operations performed to the source memory range while data is being copied from the source memory range to the destination memory. The control logic is further configured to initiate copying data associated with the tracked write operations to the destination memory.

公开(公告)号：US10067847B1

公开(公告)日：2018-09-04

申请号：US14848139

申请日：2015-09-08

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Itai Avron

IPC: G06F11/30 ,  G06F11/34

Abstract: Disclosed herein is a performance monitor for a functional block of a system, the performance monitor comprising a counter circuit, wherein the counter circuit includes a programmable time window counter configured to determine an adjustable counting period, and an event counter coupled to the time window counter. The event counter is configured to count a number of occurrences of an event occurring in the functional block during the counting period, and record the number of occurrences of the event during the counting period and generate an output trigger signal when the number of occurrences of the event during the counting period is outside of a programmable threshold band, or after receiving an input trigger signal from a cross trigger network triggered by other performance monitors in electrical communication with the cross trigger network.

公开(公告)号：US10037257B1

公开(公告)日：2018-07-31

申请号：US15084251

申请日：2016-03-29

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Eric Jason Brandwine ,  Stephen Edward Schmidt

IPC: G06F11/30 ,  G06F13/42 ,  G06F3/06 ,  G06F21/57 ,  G06F21/55

CPC classification number: G06F11/3027 ,  G06F13/423 ,  G06F13/4282 ,  G06F21/55 ,  G06F21/57 ,  G06F21/85 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: Provided are methods and peripheral devices for examining local hardware and configuring a location-aware peripheral device accordingly. In some implementations, a peripheral device may be configured to examine, using a bus interface, another device connected to the bus. Examining may include determining characteristics of the other device. In some implementations, the peripheral device may further compare the determined characteristics against information derived from data stored in a memory of the peripheral device. The information may describe acceptable operating parameters for the computing system. In some implementations, the peripheral device may further determine, based on a result of the comparison, a status for the computing system. The status may indicate whether the computing system is operating within acceptable operating parameters. The status may direct an action by the peripheral device.

公开(公告)号：US10027678B1

公开(公告)日：2018-07-17

申请号：US15084367

申请日：2016-03-29

Applicant: Amazon Technologies, Inc.

Inventor： Eric Jason Brandwine ,  Adi Habusha

IPC: G06F21/62 ,  H04L29/06 ,  G06F13/42 ,  G06F13/40 ,  G06F11/30 ,  G06F11/22 ,  G06F9/4401

Abstract: Provided are systems and methods for location-aware security configuration of peripheral devices. In various implementations, a location-aware peripheral device comprises an interface and a configuration engine. The interface may communicatively couple the peripheral device to a computing system. The configuration engine may be configured to, upon powering on in the computing system, detect a characteristic of the computing system. In some implementations, the configuration engine may further select a trust level for the computing system. In some implementations, selecting a trust level may include using the detected characteristic to identify a profile stored on the peripheral device. The profile may describe a pre-determined computing system. The configuration engine may further be configured to program the peripheral device with a configuration that is associated with the selected trust level. The configuration may program a feature of the peripheral device.

公开(公告)号：US09928207B1

公开(公告)日：2018-03-27

申请号：US14869107

申请日：2015-09-29

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Nafea Bshara ,  Itay Poleg ,  Erez Izenberg ,  Guy Nakibly ,  Matthew Shawn Wilson

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/404 ,  G06F13/4221

Abstract: Provided are systems and methods for generating transactions with a configurable port. In some implementations, a peripheral device is provided. The peripheral device comprises a configurable port. In some implementations, the configurable port may be configured to receive a first transaction. In these implementations, the first transactions may include an address. The address may include a transaction attribute. In some implementations, the configurable port may extract the transaction attribute and a transaction address from the address. The configurable port may further generate a second transaction that includes the transaction attribute and the transaction address. The configurable port may also transmit the second transaction.

公开(公告)号：US20150356013A1

公开(公告)日：2015-12-10

申请号：US14829410

申请日：2015-08-18

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC: G06F12/08 ,  G11C7/10

CPC classification number: G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

Abstract translation: 一种用于写入数据的方法，所述方法可以包括：由接口模块接收或生成用于对数据单元执行第一地址的相干写操作的数据单元相干写入请求; 通过接口模块和包括高速缓存和高速缓存控制器的电路接收指示存储在第一地址的内容的最新版本被存储在高速缓存中的高速缓存一致性指示符; 并且由所述接口模块指示所述高速缓存控制器使存储所述第一地址的最新版本的所述高速缓存的高速缓存行无效，而不将所述第一地址处存储的所述内容的最新版本从所述高速缓存发送到存储器模块 如果数据单元的长度等于高速缓存线的长度，则与缓存不同。