公开(公告)号：US09171832B2

公开(公告)日：2015-10-27

申请号：US13902729

申请日：2013-05-24

Applicant: Analog Devices, Inc.

Inventor： Javier Alejandro Salcedo ,  Karl Sweetland

IPC: H02H9/04 ,  H01L21/331 ,  H01L29/73 ,  H02H9/00 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7436

Abstract: The disclosed technology relates to an apparatus for protection against transient electrical events. In one aspect, the apparatus includes an analog switch with high bipolar blocking voltage comprising a first p-type well region, a second p-type well region, a first n-type well region disposed between the first and second p-type well regions, and a deep n-type well region surrounding the first p-type well region, the second p-type well region, and the first n-type well region. The apparatus additionally includes a first native n-type region disposed between the first p-type well region the n-type well region and a second native n-type region disposed between the second p-type well region and n-type well region. The apparatus is configured such that the first p-type well region serves as an emitter/collector of a bidirectional PNP bipolar transistor. In addition, the apparatus is configured such that the first native n-type region, the first n-type well region, and the second native n-type region serves as a base of the bidirectional PNP bipolar transistor. Furthermore, the apparatus is configured such that the second p-type well region is configured as a collector/emitter of the bidirectional PNP bipolar transistor.

Abstract translation: 所公开的技术涉及用于防止瞬时电气事件的装置。 一方面，该装置包括具有高双极性阻断电压的模拟开关，包括第一p型阱区，第二p型阱区，设置在第一和第二p型阱区之间的第一n型阱区 以及围绕第一p型阱区域，第二p型阱区域和第一n型阱区域的深n型阱区域。 该装置还包括设置在第一p型阱区n型阱区和设置在第二p型阱区与n型阱区之间的第二天然n型区之间的第一天然n型区。 该装置被配置为使得第一p型阱区域用作双向PNP双极晶体管的发射极/集电极。 此外，该装置被配置为使得第一天然n型区域，第一n型阱区域和第二天然n型区域用作双向PNP双极晶体管的基极。 此外，该装置被配置为使得第二p型阱区被配置为双向PNP双极晶体管的集电极/发射极。

公开(公告)号：US20150115317A1

公开(公告)日：2015-04-30

申请号：US14593477

申请日：2015-01-09

Applicant: Analog Devices, Inc.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H01L27/02 ,  H01L21/8222

CPC classification number: H01L27/0262 ,  H01L21/8222 ,  H01L27/0259

Abstract: Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.

Abstract translation: 提供了精密混合信号电子电路保护的装置和方法。 在一个实施例中，一种装置包括p阱，n阱，多有源二极管结构，p型有源区和n型有源区。 多极二极管结构形成在n阱上，p型有源区形成在多功能二极管结构的第一侧上的n阱中，并且n型有源区沿着 在多活性二极管结构的第二侧上的p阱和n阱的边界。 在瞬态电气事件期间，该装置被配置为提供穿过多功能二极管结构之间和之下的导电路径，以便于在n型有源区域中注入载流子。 保护装置还可以包括在p阱上形成的另一个多有源二极管结构，以进一步增强对n型有源区的载流子注入。

公开(公告)号：US09006782B2

公开(公告)日：2015-04-14

申请号：US13757588

申请日：2013-02-01

Applicant: Analog Devices, Inc.

Inventor： Javier Alejandro Salcedo

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/735 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L29/66378 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/735 ,  H01L29/78 ,  H01L29/861

Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply. The third thyristor protection structure and the third diode protection structure are synthesized as part of the integrated circuit interface and can share at least a portion of the wells and/or diffusion regions associated with the first and second thyristor protection structures.

Abstract translation: 具有集成电源钳位的保护电路架构及其形成方法在此提供。 在一些实施方式中，集成电路接口保护装置包括第一二极管保护结构和在信号引脚和电源高电源之间并联电连接的第一晶闸管保护结构。 此外，保护装置包括第二二极管保护结构和在信号引脚和电源低电源之间并联电连接的第二晶闸管保护结构。 此外，保护装置包括在电源高电源和电源低电源之间并联电连接的第三二极管保护结构和第三晶闸管保护结构。 第三晶闸管保护结构和第三二极管保护结构被合成为集成电路接口的一部分，并且可以共享与第一和第二晶闸管保护结构相关联的阱和/或扩散区域的至少一部分。

公开(公告)号：US08860080B2

公开(公告)日：2014-10-14

申请号：US13754200

申请日：2013-01-30

Applicant: Analog Devices, Inc.

Inventor： Javier Alejandro Salcedo

IPC: H01L29/66 ,  H01L21/322 ,  H01L27/06

CPC classification number: H01L29/66378 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/735 ,  H01L29/78 ,  H01L29/861

Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply. The third thyristor protection structure and the third diode protection structure are synthesized as part of the integrated circuit interface and can share at least a portion of the wells and/or diffusion regions associated with the first and second thyristor protection structures.

Abstract translation: 具有集成电源钳位的保护电路架构及其形成方法在此提供。 在一些实施方式中，集成电路接口保护装置包括第一二极管保护结构和在信号引脚和电源高电源之间并联电连接的第一晶闸管保护结构。 此外，保护装置包括第二二极管保护结构和在信号引脚和电源低电源之间并联电连接的第二晶闸管保护结构。 此外，保护装置包括在电源高电源和电源低电源之间并联电连接的第三二极管保护结构和第三晶闸管保护结构。 第三晶闸管保护结构和第三二极管保护结构被合成为集成电路接口的一部分，并且可以共享与第一和第二晶闸管保护结构相关联的阱和/或扩散区域的至少一部分。

公开(公告)号：US08796729B2

公开(公告)日：2014-08-05

申请号：US13682284

申请日：2012-11-20

Applicant: Analog Devices, Inc.

Inventor： David J Clarke ,  Javier Alejandro Salcedo ,  Brian B Moane ,  Juan Luo ,  Seamus Murnane ,  Kieran K Heffernan ,  John Twomey ,  Stephen Denis Heffernan ,  Gavin Patrick Cosgrave

IPC: H01L29/747

CPC classification number: H01L27/0248 ,  H01L27/0635 ,  H01L27/0647 ,  H01L29/0692 ,  H01L29/66386 ,  H01L29/7412 ,  H01L29/747

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Abstract translation: 提供了隔离隔离电压装置及其形成方法。 在某些实施方案中，阻断电压装置包括电连接到第一p阱的阳极端子，电连接到第一n阱的阴极端子，电连接到第二p阱的接地端子，以及n型 用于将第一p阱与p型衬底隔离的隔离层。 第一个p阱和第一个n阱作为阻塞二极管工作。 阻断电压装置还包括与形成在第一n阱，第一n阱，第一p阱以及形成在第一p阱中的N +区相关的PN +可控硅整流器（SCR） 。 另外，阻断电压装置还包括与形成在第一p阱，第一p阱，n型隔离层，第二p阱以及形成在第一p阱中的N +区域相关联的N +区域的NPNPN双向SCR 第二个p井。

公开(公告)号：US08723227B2

公开(公告)日：2014-05-13

申请号：US13625611

申请日：2012-09-24

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Shuyun Zhang

IPC: H01L29/66 ,  H01L21/336

CPC classification number: H01L21/8252 ,  H01L27/0248 ,  H01L27/0605 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7783

Abstract: A protection clamp is provided between a first terminal and a second terminal, and includes a multi-gate high electron mobility transistor (HEMT), a current limiting circuit, and a forward trigger control circuit. The multi-gate HEMT includes a drain/source, a source/drain, a first depletion-mode (D-mode) gate, a second D-mode gate, and an enhancement-mode (E-mode) gate disposed between the first and second D-mode gates. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward trigger control and the current limiting circuits are coupled between the E-mode gate and the first and second terminals, respectively. The forward trigger control circuit provides an activation voltage to the E-mode gate when a voltage of the first terminal exceeds a voltage of the second terminal by a forward trigger voltage.

Abstract translation: 在第一端子和第二端子之间提供保护夹，并且包括多门高电子迁移率晶体管（HEMT），限流电路和正向触发控制电路。 多栅极HEMT包括漏极/源极，源极/漏极，第一耗尽模式（D模式）栅极，第二D模式栅极和设置在第一和第二栅极之间的增强模式（E模式）栅极 和第二D模式门。 漏极/源极和第一D型栅极连接到第一端子，源极/漏极和第二D型栅极连接到第二端子。 正向触发控制和限流电路分别耦合在E模式门和第一和第二端子之间。 当第一端子的电压通过正向触发电压超过第二端子的电压时，正向触发控制电路向E模式栅极提供激活电压。

公开(公告)号：US20140084347A1

公开(公告)日：2014-03-27

申请号：US13625577

申请日：2012-09-24

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy ,  Shuyun Zhang

IPC: H01L27/088 ,  H01L29/778 ,  H01L21/335

CPC classification number: H01L21/8252 ,  H01L27/0248 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786

Abstract: A protection circuit including a multi-gate high electron mobility transistor (HEMT), a forward conduction control block, and a reverse conduction control block is provided between a first terminal and a second terminal. The multi-gate HEMT includes an explicit drain/source, a first depletion-mode (D-mode) gate, a first enhancement-mode (E-mode) gate, a second E-mode gate, a second D-mode gate, and an explicit source/drain. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward conduction control block turns on the second E-mode gate when a voltage difference between the first and second terminals is greater than a forward conduction trigger voltage, and the reverse conduction control block turns on the first E-mode gate when the voltage difference is more negative than a reverse conduction trigger voltage.

Abstract translation: 在第一端子和第二端子之间设置包括多栅极高电子迁移率晶体管（HEMT），正向传导控制块和反向导通控制块的保护电路。 多栅极HEMT包括显式漏极/源极，第一耗尽模式（D模式）栅极，第一增强模式（E模式）栅极，第二E模式栅极，第二D模式栅极， 和明确的源/漏。 漏极/源极和第一D型栅极连接到第一端子，源极/漏极和第二D型栅极连接到第二端子。 当第一和第二端子之间的电压差大于正向传导触发电压时，正向传导控制块导通第二E模式栅极，当反向导通控制模块的电压差 比反向传导触发电压更负。

公开(公告)号：US20130221405A1

公开(公告)日：2013-08-29

申请号：US13852883

申请日：2013-03-28

Applicant: Analog Devices, Inc.

Inventor： Javier Alejandro Salcedo ,  David Casey ,  Graham McCorkell

IPC: H01L27/06

CPC classification number: H01L27/06 ,  H01L23/60 ,  H01L27/0251 ,  H01L2924/0002 ,  H02H9/046 ,  H01L2924/00

Abstract: Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a well having an emitter and a collector region. The well has a doping of a first type, and the emitter and collector regions have a doping of a second type. The emitter region, well, and collector region are configured to operate as an emitter, base, and collector for a first transistor, respectively. The collector region is spaced away from the emitter region to define a spacing. A first spacer and a second spacer are positioned adjacent the well between the emitter and the collector. A conductive plate is positioned adjacent the well and between the first spacer and the second spacer, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type.

Abstract translation: 公开了用于电子电路保护的装置和方法。 在一个实施例中，装置包括具有发射极和集电极区的阱。 阱具有第一类型的掺杂，并且发射极和集电极区域具有第二类型的掺杂。 发射极区域，阱极和集电极区域分别被配置为用作第一晶体管的发射极，基极和集电极。 集电极区域与发射极区域间隔开以限定间隔。 第一间隔件和第二间隔件位于发射器和收集器之间的阱附近。 导电板定位成邻近阱并且位于第一间隔件和第二间隔件之间，并且与第一间隔件相邻的掺杂，第二间隔件和板基本上由第一类型组成。