公开(公告)号：US07528027B1

公开(公告)日：2009-05-05

申请号：US12054727

申请日：2008-03-25

申请人： Huilong Zhu ,  Mahender Kumar ,  Dan M. Mocuta ,  Ravikumar Ramachandran ,  Wenjuan Zhu

发明人： Huilong Zhu ,  Mahender Kumar ,  Dan M. Mocuta ,  Ravikumar Ramachandran ,  Wenjuan Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/84 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66772

摘要： An SOI CMOS structure includes a v-shape trench in a pFet region. The v-shape trench has a surface in a (111) plane and extends into an SOI layer in the pFet region. A layer, such as a gate oxide or high-k material, is formed in the v-shape trench. Poly-Si is deposited on top of the layer.

摘要翻译： SOI CMOS结构包括pFet区域中的v形沟槽。 V形沟槽具有（111）面中的表面并延伸到pFet区域中的SOI层。 在V形沟槽中形成诸如栅极氧化物或高k材料的层。 多晶硅沉积在层的顶部。

公开(公告)号：US20090072400A1

公开(公告)日：2009-03-19

申请号：US11856839

申请日：2007-09-18

申请人： Huilong Zhu ,  James J. Heaps-Nelson ,  Mahender Kumar ,  Christine Norris ,  Ravikumar Ramachandran

发明人： Huilong Zhu ,  James J. Heaps-Nelson ,  Mahender Kumar ,  Christine Norris ,  Ravikumar Ramachandran

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76847 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a contact in two or more portions and a contact so formed are disclosed. One method includes providing a device including a silicide region; and forming a contact to the silicide region by: first forming a lower contact portion to the silicide region through a first dielectric layer, and second forming an upper contact portion to the lower contact portion through a second dielectric layer over the first dielectric layer. A contact may include a first contact portion contacting a silicide region, the first contact portion having a width less than 100 nm; and a second contact portion coupled to the first contact portion from above, the second contact portion having a width greater than the width of the first contact portion.

摘要翻译： 公开了在两个或多个部分形成接触的方法和如此形成的接触。 一种方法包括提供包括硅化物区域的器件; 以及通过以下步骤形成与所述硅化物区的接触：首先通过第一介电层形成到所述硅化物区的下接触部分，以及通过所述第一电介质层上的第二电介质层，在所述下接触部分形成上接触部分。 接触可以包括接触硅化物区域的第一接触部分，第一接触部分具有小于100nm的宽度; 以及从上方联接到所述第一接触部分的第二接触部分，所述第二接触部分的宽度大于所述第一接触部分的宽度。

公开(公告)号：US07270130B2

公开(公告)日：2007-09-18

申请号：US10685684

申请日：2003-10-15

申请人： Ravikumar Ramachandran ,  David Lee Rath

发明人： Ravikumar Ramachandran ,  David Lee Rath

IPC分类号： B08B3/12

CPC分类号： H01L21/02052 ,  B08B3/12 ,  C11D1/02 ,  C11D1/38 ,  C11D7/241 ,  C11D7/261 ,  C11D11/0047 ,  H01L21/67057 ,  Y10S134/902

摘要： The present invention provides a method for cleaning semiconductor devices through heterogeneous nucleation of cavitation bubbles. Heterogeneous nucleation is performed by applying sonic energy to a cleaning solution and a phase material in order to remove unwanted particles from semiconductor devices. A surfactant may be added to the phase material and the cleaning solution.

摘要翻译： 本发明提供一种通过空化气泡的异质成核来清洁半导体器件的方法。 通过将声能施加到清洁溶液和相材料以便从半导体器件中去除不需要的颗粒来进行非均匀成核。 可以向相材料和​​清洁溶液中加入表面活性剂。

公开(公告)号：US07202187B2

公开(公告)日：2007-04-10

申请号：US10710257

申请日：2004-06-29

申请人： Ravikumar Ramachandran ,  James T. Kelliher ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Ravikumar Ramachandran ,  James T. Kelliher ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L21/3185 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/823864

摘要： A silicon nitride spacer material for use in forming a PFET device and a method for making the spacer includes the use of a dual-frequency plasma enhanced CVD process wherein the temperature is in the range depositing a silicon nitride layer by means of a low-temperature dual-frequency plasma enhanced CVD process, at a temperature in the range 400° C. to 550° C. The process pressure is in the range 2 Torr to 5 Torr. The low frequency power is in the range 0 W to 50 W, and the high frequency power is in the range 90 W to 110 W. The precursor gases of silane, ammonia and nitrogen flow at flow rates in the ratio 240:3200:4000 sccm. The use of the silicon nitride spacer of the invention to form a PFET device having a dual spacer results in a 10%–15% performance improvement compared to a similar PFET device having a silicon nitride spacer formed by a RTCVD process.

摘要翻译： 用于形成PFET器件的氮化硅间隔物材料和用于制造间隔物的方法包括使用双频等离子体增强CVD工艺，其中温度在通过低温下沉积氮化硅层的范围 双频等离子体增强CVD工艺，温度范围为400°C至550°C。工艺压力范围为2 Torr至5 Torr。 低频功率在0W至50W的范围内，高频功率在90W至110W的范围内。硅烷，氨和氮气的前体气体以240：3200：4000的比例流动 sccm。 与具有通过RTCVD工艺形成的氮化硅间隔物的类似PFET器件相比，使用本发明的氮化硅间隔物形成具有双间隔物的PFET器件导致10％-15％的性能提高。

公开(公告)号：US20060252197A1

公开(公告)日：2006-11-09

申请号：US11482419

申请日：2006-07-07

申请人： Bachir Dirahoui ,  Renee Mo ,  Ravikumar Ramachandran ,  Eric Solecky

发明人： Bachir Dirahoui ,  Renee Mo ,  Ravikumar Ramachandran ,  Eric Solecky

IPC分类号： H01L21/8238

CPC分类号： H01L22/12

摘要： A process implementing steps for determining encroachment of a spacer structure in a semiconductor device having thick and thin spacer regions, including a transition region formed therebetween. The method steps comprise: obtaining a line width roughness (LWR) measurement at at least one location along each thick, thin and transition spacer regions; determining a threshold LWR measurement value based on the LWR measurements; defining a region of interest (ROI) and obtaining a further LWR measurement in the ROI; comparing the LWR measurement in the ROI against the threshold LWR measurement value; and, notifying a user that either encroachment of the spacer structure is present when the LWR measurement in the ROI is below the threshold LWR measurement value, or that no encroachment of the spacer structure is present when the LWR measurement in the ROI is above the threshold LWR measurement value.

公开(公告)号：US07105398B2

公开(公告)日：2006-09-12

申请号：US10942303

申请日：2004-09-16

申请人： Bachir Dirahoui ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Eric P. Solecky

发明人： Bachir Dirahoui ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Eric P. Solecky

IPC分类号： H01L21/8238

CPC分类号： H01L22/12

摘要： A process implementing steps for determining encroachment of a spacer structure in a semiconductor device having thick and thin spacer regions, including a transition region formed therebetween. The method steps comprise: obtaining a line width roughness (LWR) measurement at at least one location along each thick, thin and transition spacer regions; determining a threshold LWR measurement value based on the LWR measurements; defining a region of interest (ROI) and obtaining a further LWR measurement in the ROI; comparing the LWR measurement in the ROI against the threshold LWR measurement value; and, notifying a user that either encroachment of the spacer structure is present when the LWR measurement in the ROI is below the threshold LWR measurement value, or that no encroachment of the spacer structure is present when the LWR measurement in the ROI is above the threshold LWR measurement value.

公开(公告)号：US20060105526A1

公开(公告)日：2006-05-18

申请号：US10904582

申请日：2004-11-17

申请人： Oh-Jung Kwon ,  Kenneth Settlemyer ,  Ravikumar Ramachandran ,  Min-Soo Kim

发明人： Oh-Jung Kwon ,  Kenneth Settlemyer ,  Ravikumar Ramachandran ,  Min-Soo Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/1087 ,  H01L29/66181

摘要： A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.

公开(公告)号：US20050153467A1

公开(公告)日：2005-07-14

申请号：US11076371

申请日：2005-03-09

申请人： Lance Genicola ,  Mark Hurley ,  Jeremy Kempisty ,  Paul Kirsch ,  Ravikumar Ramachandran ,  Suri Hedge

发明人： Lance Genicola ,  Mark Hurley ,  Jeremy Kempisty ,  Paul Kirsch ,  Ravikumar Ramachandran ,  Suri Hedge

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/51 ,  H01L21/66 ,  G01R31/26 ,  G06F19/00 ,  H01L21/336

CPC分类号： H01L21/67167 ,  H01L21/02329 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/3144 ,  H01L21/3185 ,  H01L21/67213 ,  H01L21/67253 ,  H01L29/513 ,  H01L29/518 ,  Y10T29/41

摘要： A method for monitoring a nitridation process, including: (a) providing a semiconductor substrate; (b) forming a first dielectric layer on a top surface of the substrate; (c) introducing a quantity of interfacial species into the substrate; (d) removing the first dielectric layer; (e) forming a second dielectric layer on the top surface of the substrate; (f) measuring the density of interface traps between the substrate and the second dielectric layer; (g) providing a predetermined relationship between the quantity of the interfacial species and the density of the interface traps; and (h) determining the quantity of the interfacial species introduced based on the relationship.

摘要翻译： 一种用于监测氮化工艺的方法，包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成第一电介质层; （c）将一定量的界面物质引入底物; （d）去除第一电介质层; （e）在所述衬底的顶表面上形成第二电介质层; （f）测量衬底和第二介电层之间的界面陷阱的密度; （g）提供界面物质的量与界面捕集阱的密度之间的预定关系; 和（h）基于关系确定引入的界面物质的数量。

公开(公告)号：US06858441B2

公开(公告)日：2005-02-22

申请号：US10234864

申请日：2002-09-04

申请人： Joachim Nuetzel ,  Xian J. Ning ,  Kia-Seng Low ,  Gill Yong Lee ,  Rajiv M. Ranade ,  Ravikumar Ramachandran

发明人： Joachim Nuetzel ,  Xian J. Ning ,  Kia-Seng Low ,  Gill Yong Lee ,  Rajiv M. Ranade ,  Ravikumar Ramachandran

IPC分类号： H01L23/544 ,  H01L27/22 ,  H01L21/28

CPC分类号： H01L27/222 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A method of manufacturing a resistive semiconductor memory device (100), comprising depositing an insulating layer (132) over a workpiece (30), and defining a pattern for a plurality of alignment marks (128) and a plurality of conductive lines (112) within the insulating layer (132). A conductive material is deposited over the wafer to fill the alignment mark (128) and conductive line (112) patterns. The insulating layer (132) top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer (132) and form conductive lines (112), while leaving conductive material remaining within the alignment marks (128). A masking layer (140) is formed over the conductive lines (112), and at least a portion of the conductive material is removed from within the alignment marks (128). The alignment marks (128) are used for alignment of subsequently deposited layers of the resistive memory device (100).

摘要翻译： 一种制造电阻半导体存储器件（100）的方法，包括在工件（30）上沉积绝缘层（132），并且限定用于多个对准标记（128）和多条导线（112）的图案， 在绝缘层（132）内。 导电材料沉积在晶片上以填充对准标记（128）和导线（112）图案。 绝缘层（132）顶表面被化学机械抛光以从绝缘层（132）去除多余的导电材料并形成导电线（112），同时留下导电材料留在对准标记（128）内。 掩模层（140）形成在导电线（112）之上，并且导电材料的至少一部分从对准标记（128）内移除。 对准标记（128）用于电阻式存储器件（100）的后续沉积层的对准。

公开(公告)号：US06716734B2

公开(公告)日：2004-04-06

申请号：US09965092

申请日：2001-09-28

申请人： Mihel Seitz ,  Ravikumar Ramachandran

发明人： Mihel Seitz ,  Ravikumar Ramachandran

IPC分类号： H01L213205

CPC分类号： H01L21/31687 ,  H01L21/02258 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/32105

摘要： In a method of making a W/WN/Poly-Gatestack, the improvement of providing low temperature sidewall oxidation to affect less outdiffusion of dopant implants near the surface to allow more margin in small groundrule device design for a support device, comprising: depositing a silicon layer on a substrate; forming a W-containing nitride layer on the deposited silicon; depositing a W layer on the W-containing nitride layer to form a W/WN/silicon stack; and performing a gatesidewall anodic oxidation by affecting a mask open to enable contacting W at its wafer edge and putting the gatestack on the positive potential or anode and the counter electrode on the negative potential.

摘要翻译： 在制造W / WN / Poly-Gatestack的方法中，改进提供低温侧壁氧化以影响表面附近的掺杂剂注入的较少的扩散，以允许用于支撑装置的小的基础设备设计中的更多余量，包括： 硅层; 在沉积的硅上形成含W的氮化物层;在W含氮化物层上沉积W层以形成W / WN /硅堆叠; 并且通过影响掩模开口来执行栅极壁阳极氧化，以使其能够在其晶片边缘处接触W并将盖板放在正电位或阳极上，并将反电极放置在负电位上。