公开(公告)号：US12019269B2

公开(公告)日：2024-06-25

申请号：US17987485

申请日：2022-11-15

Applicant: Ayar Labs, Inc.

Inventor： Roy Edward Meade ,  Chong Zhang ,  Haiwei Lu ,  Chen Li

IPC: G02B6/122 ,  G02B6/12

CPC classification number: G02B6/1225 ,  G02B6/12011 ,  G02B2006/1213

Abstract: A multi-chip package assembly includes a substrate, a first semiconductor chip attached to the substrate, and a second semiconductor chip attached to the substrate, such that a portion of the second semiconductor chip overhangs an edge of the substrate. A first v-groove array for receiving a plurality of optical fibers is present within the portion of the second semiconductor chip that overhangs the edge of the substrate. An optical fiber assembly including the plurality of optical fibers is positioned and secured within the first v-groove array of the second semiconductor chip. The optical fiber assembly includes a second v-groove array configured to align the plurality of optical fibers to the first v-groove array of the second semiconductor chip. An end of each of the plurality of optical fibers is exposed for optical coupling within an optical fiber connector located at a distal end of the optical fiber assembly.

公开(公告)号：US20240187110A1

公开(公告)日：2024-06-06

申请号：US18419461

申请日：2024-01-22

Applicant: Ayar Labs, Inc.

Inventor： Roy Edward Meade ,  Vladimir Stojanovic ,  Chen Sun ,  Mark Wade ,  Hugo Saleh ,  Charles Wuischpard

IPC: H04B10/80 ,  G02B6/42 ,  G11C5/04 ,  G11C5/06 ,  G11C5/14 ,  G11C11/42 ,  H04B10/516

CPC classification number: H04B10/80 ,  G02B6/4249 ,  G02B6/4274 ,  G11C5/04 ,  G11C5/06 ,  G11C5/141 ,  G11C11/42 ,  H04B10/516

Abstract: A remote memory system includes a substrate of a multi-chip package, an integrated circuit chip connected to the substrate, and an electro-optical chip connected to the substrate. The integrated circuit chip includes a high-bandwidth memory interface. An electrical interface of the electro-optical chip is electrically connected to the high-bandwidth memory interface. A photonic interface of the electro-optical chip is configured to optically connect with an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals received through the electrical interface from the high-bandwidth interface into outgoing optical data signals. The optical macro transmits the outgoing optical data signals through the photonic interface to the optical link. The optical macro also converts incoming optical data signals received through the photonic interface into incoming electrical data signals. The optical macro transmits the incoming electrical data signals through the electrical interface to the high-bandwidth memory interface.

公开(公告)号：US20240176081A1

公开(公告)日：2024-05-30

申请号：US18432768

申请日：2024-02-05

Applicant: Ayar Labs, Inc.

Inventor： Chong Zhang ,  Roy Edward Meade

IPC: G02B6/42 ,  G02B6/30 ,  G02B6/43 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18 ,  H05K1/02

CPC classification number: G02B6/42 ,  G02B6/30 ,  G02B6/4214 ,  G02B6/4249 ,  G02B6/4274 ,  H01L23/5389 ,  H01L25/18 ,  H01L25/50 ,  H05K1/0274 ,  G02B6/428 ,  G02B6/43 ,  H05K2201/10121

Abstract: A vertical integrated photonics chiplet assembly includes a package substrate and an external device connected to a top surface of the package substrate. A photonics chip is disposed within the package substrate The photonics chip includes optical coupling devices positioned at a top surface of the photonics chip. A plurality of conductive via structures are disposed within the package substrate in electrical connection with electrical circuits within the photonics chip. The plurality of conductive via structures are electrically connected through the package substrate to the external device. An opening is formed through the top surface of the substrate to expose a portion of the top surface of the photonics chip at which the optical coupling devices are positioned. An optical fiber array is disposed and secured within the opening such that a plurality of optical fibers of the optical fiber array optically couple to the optical coupling devices.

公开(公告)号：US11916602B2

公开(公告)日：2024-02-27

申请号：US17175677

申请日：2021-02-14

Applicant: Ayar Labs, Inc.

Inventor： Roy Edward Meade ,  Vladimir Stojanovic ,  Chen Sun ,  Mark Wade ,  Hugo Saleh ,  Charles Wuischpard

IPC: H04B10/00 ,  H04B10/80 ,  H04B10/516 ,  G11C5/04 ,  G11C5/06 ,  G11C11/42 ,  G02B6/42 ,  G11C5/14 ,  H04J14/00

CPC classification number: H04B10/80 ,  G02B6/4249 ,  G02B6/4274 ,  G11C5/04 ,  G11C5/06 ,  G11C5/141 ,  G11C11/42 ,  H04B10/516

Abstract: A remote memory system includes a substrate of a multi-chip package, an integrated circuit chip connected to the substrate, and an electro-optical chip connected to the substrate. The integrated circuit chip includes a high-bandwidth memory interface. An electrical interface of the electro-optical chip is electrically connected to the high-bandwidth memory interface. A photonic interface of the electro-optical chip is configured to optically connect with an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals received through the electrical interface from the high-bandwidth interface into outgoing optical data signals. The optical macro transmits the outgoing optical data signals through the photonic interface to the optical link. The optical macro also converts incoming optical data signals received through the photonic interface into incoming electrical data signals. The optical macro transmits the incoming electrical data signals through the electrical interface to the high-bandwidth memory interface.

公开(公告)号：US20240014904A1

公开(公告)日：2024-01-11

申请号：US18471139

申请日：2023-09-20

Applicant: Ayar Labs, Inc.

Inventor： Chen Sun ,  Roy Edward Meade ,  Mark Wade ,  Alexandra Wright ,  Vladimir Stojanovic ,  Rajeev Ram ,  Milos Popovic ,  Derek Van Orden ,  Michael Davenport

IPC: H04B10/50 ,  H01S5/40 ,  H01S5/026 ,  H04B10/80 ,  H01S5/02325

CPC classification number: H04B10/504 ,  H01S5/4012 ,  H01S5/4087 ,  H01S5/0268 ,  H04B10/801 ,  H04B10/506 ,  H01S5/02325 ,  H01S5/02476

Abstract: An interposer device includes a substrate that includes a laser source chip interface region, a silicon photonics chip interface region, an optical amplifier module interface region. A fiber-to-interposer connection region is formed within the substrate. A first group of optical conveyance structures is formed within the substrate to optically connect a laser source chip to a silicon photonics chip when the laser source chip and the silicon photonics chip are interfaced to the substrate. A second group of optical conveyance structures is formed within the substrate to optically connect the silicon photonics chip to an optical amplifier module when the silicon photonics chip and the optical amplifier module are interfaced to the substrate. A third group of optical conveyance structures is formed within the substrate to optically connect the optical amplifier module to the fiber-to-interposer connection region when the optical amplifier module is interfaced to the substrate.

公开(公告)号：US11867944B2

公开(公告)日：2024-01-09

申请号：US17701072

申请日：2022-03-22

Applicant: Ayar Labs, Inc.

Inventor： Roy Edward Meade ,  Chen Sun ,  Shahab Ardalan ,  John Fini ,  Forrest Sedgwick

IPC: G02B6/13 ,  G02B6/12 ,  H01L21/66 ,  G01M11/00

CPC classification number: G02B6/12004 ,  G01M11/31 ,  G02B6/13 ,  H01L22/20 ,  H01L22/30 ,  G02B2006/12107 ,  G02B2006/12121 ,  G02B2006/12145 ,  G02B2006/12147 ,  G02B2006/12164

Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.

公开(公告)号：US20230343655A1

公开(公告)日：2023-10-26

申请号：US18346555

申请日：2023-07-03

Applicant: Ayar Labs, Inc.

Inventor： Roy Edward Meade ,  Anatol Khilo ,  Forrest Sedgwick ,  Alexandra Wright

IPC: H01L21/66 ,  H04B10/073 ,  G02B6/12 ,  G02B6/13 ,  G01R31/3185

CPC classification number: H01L22/30 ,  H04B10/0731 ,  G02B6/12 ,  G02B6/13 ,  G01R31/318511 ,  G02B6/0028

Abstract: A semiconductor wafer includes a semiconductor chip that includes a photonic device. The semiconductor chip includes an optical fiber attachment region in which an optical fiber alignment structure is to be fabricated. The optical fiber alignment structure is not yet fabricated in the optical fiber attachment region. The semiconductor chip includes an in-plane fiber-to-chip optical coupler positioned at an edge of the optical fiber attachment region. The in-plane fiber-to-chip optical coupler is optically connected to the photonic device. A sacrificial optical structure is optically coupled to the in-plane fiber-to-chip optical coupler. The sacrificial optical structure includes an out-of-plane optical coupler configured to receive input light from a light source external to the semiconductor chip. At least a portion of the sacrificial optical structure extends through the optical fiber attachment region.

公开(公告)号：US11799554B2

公开(公告)日：2023-10-24

申请号：US17866482

申请日：2022-07-16

Applicant: Ayar Labs, Inc.

Inventor： Chen Sun ,  Roy Edward Meade ,  Mark Wade ,  Alexandra Wright ,  Vladimir Stojanovic ,  Rajeev Ram ,  Milos Popovic ,  Derek Van Orden ,  Michael Davenport

IPC: H04B10/50 ,  H01S5/40 ,  H01S5/026 ,  H04B10/80 ,  H01S5/02325 ,  H01S5/024 ,  H01S5/50 ,  G02B6/42

CPC classification number: H04B10/504 ,  H01S5/0268 ,  H01S5/02325 ,  H01S5/4012 ,  H01S5/4087 ,  H04B10/506 ,  H04B10/801 ,  G02B6/42 ,  H01S5/02476 ,  H01S5/50

Abstract: An interposer device includes a substrate that includes a laser source chip interface region, a silicon photonics chip interface region, an optical amplifier module interface region. A fiber-to-interposer connection region is formed within the substrate. A first group of optical conveyance structures is formed within the substrate to optically connect a laser source chip to a silicon photonics chip when the laser source chip and the silicon photonics chip are interfaced to the substrate. A second group of optical conveyance structures is formed within the substrate to optically connect the silicon photonics chip to an optical amplifier module when the silicon photonics chip and the optical amplifier module are interfaced to the substrate. A third group of optical conveyance structures is formed within the substrate to optically connect the optical amplifier module to the fiber-to-interposer connection region when the optical amplifier module is interfaced to the substrate.

公开(公告)号：US11705972B2

公开(公告)日：2023-07-18

申请号：US17583967

申请日：2022-01-25

Applicant: Ayar Labs, Inc.

Inventor： Roy Edward Meade ,  Vladimir Stojanovic ,  Chen Sun ,  Mark Wade ,  Hugo Saleh ,  Charles Wuischpard

IPC: G11C5/04 ,  G11C5/06 ,  G11C5/14 ,  G11C11/42 ,  H04B10/80 ,  H04B10/516 ,  G02B6/42

CPC classification number: H04B10/80 ,  G02B6/4249 ,  G02B6/4274 ,  G11C5/04 ,  G11C5/06 ,  G11C5/141 ,  G11C11/42 ,  H04B10/516

Abstract: A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.

公开(公告)号：US11563506B2

公开(公告)日：2023-01-24

申请号：US17410443

申请日：2021-08-24

Applicant: Ayar Labs, Inc.

Inventor： Vladimir Stojanovic ,  Alexandra Wright ,  Chen Sun ,  Mark Wade ,  Roy Edward Meade

IPC: H04J14/02 ,  H04Q11/00 ,  H04B10/50 ,  G02B6/293 ,  G02B6/43 ,  G02B6/42

Abstract: A TORminator module is disposed with a switch linecard of a rack. The TORminator module receives downlink electrical data signals from a rack switch. The TORminator module translates the downlink electrical data signals into downlink optical data signals. The TORminator module transmits multiple subsets of the downlink optical data signals through optical fibers to respective SmartDistributor modules disposed in respective racks. Each SmartDistributor module receives multiple downlink optical data signals through a single optical fiber from the TORminator module. The SmartDistributor module demultiplexes the multiple downlink optical data signals and distributes them to respective servers. The SmartDistributor module receives multiple uplink optical data signals from multiple servers and multiplexes them onto a single optical fiber for transmission to the TORminator module. The TORminator module coverts the multiple uplink optical data signals to multiple uplink electrical data signals, and transmits the multiple uplink electrical data signals to the rack switch.